Low power retention flip-flops

• US 7,908,500 B2
• Filed: 10/01/2007
• Issued: 03/15/2011
• Est. Priority Date: 10/01/2007
• Status: Active Grant

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Shannon, Donelson A., Vogel, Gabriel, Westwick, Alan L., Wei, Dazhi, Guo, Xiaoling
• Primary Examiner(s): Cao; Chun
• Application Number:
  US11/865,661
• Publication Number:
  US 20090089599A1
• Time in Patent Office: 1,261 Days
• Field of Search: 713/320, 713/323, 327/202
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A microcontroller includes a processing unit having a processing unit having normal power mode of operation and a low power mode of operation. The processing unit further having digital circuitry connected to the processing unit having a plurality of logic circuits associated therewith for processing digital values. A plurality of retention flip-flops are associated with the digital circuitry for storing a logical state of at least one or more of the logic circuits within the digital circuitry when the processing unit enters the low power mode of operation. The plurality of retention flip flops include a first type of transistors for operating in both the low and high power modes of operation and a second type of transistors for operation only in the normal mode of operation and wherein substantially the remainder of the digital circuitry in the processing unit comprises the second type of transistors.

Claims

1. A microcontroller unit, comprising:

a processing unit having normal power mode of operation and a low power mode of operation and having;

digital circuitry connected to the processing unit having a plurality of logic circuits associated therewith for processing digital values;

a plurality of retention flip-flops associated with the digital circuitry for storing a logical state of at least one or more of the logic circuits within the digital circuitry when the processing unit enters the low power mode of operation, wherein each of the plurality of retention flip flops further comprises;

a master latch circuit comprised of thin oxide transistors for latching the digital circuit values in the normal power mode of operation;

a driver circuit comprised of the thin oxide transistors for driving an output of the retention flip-flops in the normal power mode of operation; and

a slave latch circuit for latching the digital circuit values in the low power mode of operation, the slave latch circuit including both the thin oxide transistors and thick oxide transistors, the thick oxide transistors for latching the digital circuit values in the low power mode of operation and both the thick oxide transistors and the thin oxide transistor for use in latching the digital circuit values in the normal power mode of operation.

2. The microcontroller unit of claim 1, wherein the thin oxide transistors comprise core transistors and the thick oxide transistors comprise input/output transistors.

3. The microprocessor unit of claim 1 further including a switch connected between the master latch and the slave latch for disconnecting the master latch from the slave latch in the low power mode of operation.

4. The microprocessor unit of claim 1 wherein system power is provided to the retention flip-flop in the normal power mode of operation and the system power is removed from the retention flip-flop in the low power mode of operation.

5. The microcontroller unit of claim 1, wherein the retention flip flops are integral and part of the digital circuitry utilized in the processing of digital values.

6. The microcontroller unit of claim 1, wherein the retention flip flops are disposed in between data and input to an associated one of the logic circuits on an output of an associated one of the logic circuits.

7. A microcontroller unit, comprising:

a processing unit having normal power mode of operation wherein system power is provided and a low power mode of operation wherein system power is removed and having;

digital circuitry connected to the processing unit having a plurality of logic circuits associated therewith for processing digital values;

a plurality of retention flip-flops associated with the digital circuitry for storing a logical state of at least one or more of the logic circuits within the digital circuitry when the processing unit enters the low power mode of operation wherein system power is removed, wherein each of the plurality of retention flip flops further comprises;

a master latch circuit comprised of thin oxide transistors for latching the digital circuit values in the normal power mode of operation when system power is provided;

a driver circuit comprised of the thin oxide transistors for driving an output of the retention flip-flops in the normal power mode of operation when system power is provided;

a slave latch circuit for latching the digital circuit values in the low power mode of operation, when system power is removed, the slave latch circuit including both the thin oxide transistors and thick oxide transistors, the thick oxide transistors for latching the digital circuit values in the low power mode of operation when system power is removed and both the thick oxide transistors and the thin oxide transistor for use in latching the digital circuit values in the normal power mode of operation when system power is provided; and

a switch for disconnecting the master latch from the slave latch in the low power mode of operation when system power is removed.

8. The microcontroller unit of claim 7, wherein the retention flip flops are integral and part of the digital circuitry utilized in the processing of digital values.

9. The microcontroller unit of claim 7, wherein the retention flip flops are disposed in between data and input to an associated one of the logic circuits on an output of an associated one of the logic circuits.

10. A retention flip-flop circuit, comprising:

a master latch circuit comprised of thin oxide transistors for latching the digital circuit values in a normal power mode of operation;

a driver circuit comprised of the thin oxide transistors for driving an output of the retention flip-flops in the normal power mode of operation; and

a slave latch circuit for latching the digital circuit values in a low power mode of operation, the slave latch circuit including both the thin oxide transistors and thick oxide transistors, the thick oxide transistors for latching the digital circuit values in the low power mode of operation and both the thick oxide transistors and the thin oxide transistor for use in latching the digital circuit values in the normal power mode of operation.

11. The retention flip-flop circuit of claim 10, wherein the thin oxide transistors comprise core transistors and thick oxide transistors comprise input/output transistors.

12. The retention flip-flop of claim 10 further including a switch connected between the master latch and the slave latch for disconnecting the master latch from the slave latch in the low power mode of operation.

13. The retention flip-flop of claim 10 wherein system power is provided to the retention flip-flop in the normal power mode of operation and the system power is removed from the retention flip-flop in the low power mode of operation.