Method, system and computer program product for failure analysis implementing automated comparison of multiple reference models

• US 7,908,518 B2
• Filed: 02/08/2008
• Issued: 03/15/2011
• Est. Priority Date: 02/08/2008
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kapadia, Vimal M., West, Patrick M. Jr., Krygowski, Christopher A., Slegel, Timothy J
• Primary Examiner(s): Chu; Gabriel L
• Application Number:
  US12/028,039
• Publication Number:
  US 20090204924A1
• Time in Patent Office: 1,131 Days
• Field of Search: 714/28, 714/29
• US Class Current: 714/28
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation

Abstract

System, method and computer program products for failure analysis implementing automated comparison of multiple reference models. An exemplary embodiment includes a method for failure analysis for an instruction set implementation in a computer system, the method including running a test-case in a first and a second model, determining if the test case failed in the first model and determining if the test case failed in the second model.

Claims

1. A method for failure analysis for an instruction set implementation in a computer system, the method comprising:

running a test-case in a simulation model and a reference model;

in response to a failure in at least one of the simulation model and the reference model, determining if the test case failed in the simulation model;

in response to a failure in the simulation model, determining if the test case failed in the reference model; and

in response to the test case passing in the simulation model, determining that the reference model is a source of failure for the instruction set.

2. The method as claimed in claim 1 further comprising in response to the test-case passing in the reference model, determining that at least one of a hardware implementation of the instruction set and the simulation model is a source of failure of the instruction set.

3. The method as claimed in claim 1 further comprising in response to the test case failing in the reference model and the test case failing in the simulation model, determining that at least one of a firmware implementation of the instruction set and the test case is a source of a failure of the instruction set.

4. The method as claimed in claim 1 wherein the simulation model tests hardware and firmware execution of the instruction set.

5. The method as claimed in claim 4 wherein the reference model emulates operation of the hardware.

6. The method as claimed in claim 1 further comprising generating simulation and reference model results.

7. The method as claimed in claim 1 further comprising generating firmware a source code listing and a hardware state listing.

8. A computer program product for failure analysis for an instruction set implementation in a computer system, the computer program product including a non-transitory computer readable medium having instructions for causing a computer to implement a method, comprising:

running a test-case in a simulation model and a reference model;

in response to a failure in at least one of the simulation model and the reference model, determining if the test case failed in the simulation model;

in response to a failure in the simulation model, determining if the test case failed in the reference model; and

in response to the test case passing in the simulation model, determining that the reference model is a source of failure for the instruction set.

9. The computer program product as claimed in claim 8 wherein the method further comprises in response to the test-case passing in the reference model, determining that at least one of a hardware implementation of the instruction set and the simulation model is a source of failure of the instruction set.

10. The computer program product as claimed in claim 8 wherein the method further comprises in response to the test case failing in the reference model and the test case failing in the simulation model, determining that at least one of a firmware implementation of the instruction set and the test case is a source of a failure of the instruction set.

11. The computer program product as claimed in claim 8 wherein the simulation model tests hardware and firmware execution of the instruction set.

12. The computer program product as claimed in claim 11 wherein the reference model emulates operation of the hardware.

13. The computer program product as claimed in claim 8 wherein the method further comprises generating simulation and reference model results.

14. The computer program product as claimed in claim 8 wherein the method further comprises generating a firmware source code listing and a hardware state listing.

15. A system for failure analysis for an instruction set implementation, the system comprising:

a processor configured to;

run a test-case in a simulation model and a reference model;

in response to a failure in at least one of the simulation model and the reference model, determine if the test case failed in the simulation model;

in response to a failure in the simulation model, determine if the test case failed in the reference model; and

in response to the test case passing in the simulation model, determine that the reference model is a source of failure for the instruction set.

16. The system as claimed in claim 15 wherein the processor is further configured to in response to the test-case passing in the reference model, determine that at least one of a hardware implementation of the instruction set and the simulation model is a source of failure of the instruction set.

17. The system as claimed in claim 15 wherein the processor is further configured to in response to the test case failing in the reference model and the test case failing in the simulation model, determine that at least one of a firmware implementation of the instruction set and the test case is a source of a failure of the instruction set.

18. The system as claimed in claim 15 wherein the simulation model tests hardware and firmware execution of the instruction set.

19. The system as claimed in claim 18 wherein the reference model emulates operation of the hardware.

20. The system as claimed in claim 15 wherein the processor is further configured to generate simulation model results, reference model results, a firmware source code listing and a hardware state listing.