Software/hardware partitioning program and method

• US 7,908,592 B2
• Filed: 10/04/2006
• Issued: 03/15/2011
• Est. Priority Date: 04/12/2006
• Status: Expired due to Fees

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Tatsuoka, Masato, Ike, Atsushi
• Primary Examiner(s): Zhen; Wei Y
• Assistant Examiner(s): CHOW, CHIH CHING
• Application Number:
  US11/538,601
• Publication Number:
  US 20070245326A1
• Time in Patent Office: 1,623 Days
• Field of Search: 717/140, 717/131, 716/2, 716/3, 716/7, 703/2
• US Class Current: 717/131
• CPC Class Codes: G06F 2115/02 System on chip [SoC] design
• CPC Class Codes: G06F 2117/08 HW-SW co-design, e.g. HW-SW partitioning
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation
• CPC Class Codes: G06F 8/44 Encoding

Abstract

A software/hardware (SW/HW) partitioning and evaluating program allows a computer to perform a procedure of compiling a source code in which a mark is added to a portion to be executed by hardware, a procedure of generating an executable program for a simulator of CPU on a system-on-chip (SoC), a procedure of storing in memory an execution result of the executable program, and a procedure of evaluating an SW/HW partition based on the execution result.

Claims

1. A computer-readable storage medium that stores a software/hardware partitioning evaluating program used to direct a computer to partition a source code into a software unit and a hardware unit to realize an application for a system-on chip (SoC), wherein the evaluating program enables the computer to execute:

compiling a source code corresponding to the application, in which a mark is added to the source code to indicate a start point and an endpoint of a hardware unit, the hardware unit representing source code to be executed by hardware, and generating a model of the hardware unit as a process portion to be realized by hardware, and an executable program for a simulator of a central processing unit used to realize the application

processing, using the simulator, the executable program using an execution process that executes the hardware unit through an object function call to the model of the hardware unit and an execution process that executes a software unit without the object function call, the software unit representing the source code excluding the hardware unit;

storing in memory an execution result of the executable program using the simulator including a result obtained by execution performed by calling a model of the hardware unit; and

evaluating, based on the execution result stored in the memory, a partition between the software unit and the hardware unit corresponding to the mark added to the hardware unit, wherein the execution result includes at least a processing time of the hardware unit and at least a processing time of the software unit.

2. The computer-readable storage medium according to claim 1, wherein

the simulator performs all processes corresponding to the source code of the application including a process corresponding to the model of the hardware unit in addition to a process corresponding to the software unit.

3. The computer-readable storage medium according to claim 1, wherein the computer further performs a procedure of generating an address specification file storing an address of the object function during the compilation.

4. The computer-readable storage medium according to claim 3, wherein

the address stored in the address specification file is automatically set during the compilation.

5. The computer-readable storage medium according to claim 3, wherein

the address stored in the address specification file is set corresponding to a user specification when the mark is added to the hardware unit.

6. A software/hardware partitioning evaluating method for partitioning a source code into a software unit and a hardware unit to realize an application for a system-on chip (SoC), the method comprising:

compiling a source code corresponding to the application, in which a mark is added to the source code to indicate a start point and an endpoint of a hardware unit, the hardware unit representing source code to be executed by hardware, and generating a model of a hardware unit as a process portion to be realized by hardware, and an executable program for a simulator of a central processing unit used to realize the application

processing, using the simulator, the executable program using an execution process that executes the hardware unit through an object function call to the model of the hardware unit and an execution process that executes a software unit without the object function call, the software unit representing the source code excluding the hardware unit;

storing in memory an execution result of the executable program using the simulator; and

evaluating, based on the execution result stored in the memory, a partition between the software unit and the hardware unit corresponding to the mark added to the hardware unit, wherein the execution result includes at least a processing time of the hardware unit and at least a processing time of the software unit.