Mask material conversion

• US 7,910,288 B2
• Filed: 09/01/2004
• Issued: 03/22/2011
• Est. Priority Date: 09/01/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sandhu, Gurtej, Abatchev, Mirzafer K.
• Primary Examiner(s): Chea; Thorl
• Application Number:
  US10/932,993
• Publication Number:
  US 20060046200A1
• Time in Patent Office: 2,393 Days
• Field of Search: 430/313, 430/5
• US Class Current: 430/313
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32139 using masks

Abstract

The dimensions of mask patterns, such as pitch-multiplied spacers, are controlled by controlled growth of features in the patterns after they are formed. To form a pattern of pitch-multiplied spacers, a pattern of mandrels is first formed overlying a semiconductor substrate. Spacers are then formed on sidewalls of the mandrels by depositing a blanket layer of material over the mandrels and preferentially removing spacer material from horizontal surfaces. The mandrels are then selectively removed, leaving behind a pattern of freestanding spacers. The spacers comprise a material, such as polysilicon and amorphous silicon, known to increase in size upon being oxidized. The spacers are oxidized to grow them to a desired width. After reaching the desired width, the spacers can be used as a mask to pattern underlying layers and the substrate. Advantageously, because the spacers are grown by oxidation, thinner blanket layers can be deposited over the mandrels, thereby allowing the deposition of more conformal blanket layers and widening the process window for spacer formation.

Claims

1. A method for semiconductor processing, comprising:

forming a plurality of spacers on a substrate by pitch multiplication, the spacers formed of a spacer material, wherein forming the plurality of spacers comprises;

providing a plurality of spaced-apart mandrels;

depositing a blanket layer of the spacer material on the mandrels;

anisotropically etching the spacer material to define the spacers; and

preferentially removing the mandrels;

expanding a volume of the spacer material forming the spacers by converting the spacer material to a material occupying a larger volume than the spacer material;

forming a photodefinable layer extending over the spacers; and

patterning the photodefinable layer.

2. The method of claim 1, wherein expanding a volume of the spacer material forming the spacers comprises expanding the blanket layer of spacer material during forming a plurality of spacers by pitch multiplication.

3. The method of claim 2, further comprising:

etching horizontal surfaces to form spacers from the blanket layer of spacer material after expanding the spacer material.

4. The method of claim 2, wherein forming a plurality of spacers comprises:

expanding the spacer material after anisotropically etching horizontal surfaces.

5. The method of claim 1, wherein converting the spacer material to the second material comprises oxidizing the spacer material forming the spacers.

6. The method of claim 1, wherein converting the spacer material to the second material comprises nitriding the spacer material forming the spacers.

7. The method of claim 1, further comprising exposing an underlying layer to reactants through openings between the spacers.

8. The method of claim 7, wherein the reactants are etchants.

9. The method of claim 8, wherein exposing an underlying layer comprises etching amorphous carbon.

10. The method of claim 8, wherein exposing an underlying layer comprises etching a conductive material in the substrate.

11. The method of claim 1, further comprising trimming the spacers after expanding a volume of material forming the spacers.

12. The method of claim 1, wherein the spacers comprise polysilicon or amorphous silicon.

13. The method of claim 1, wherein expanding the volume of the spacer material enlarges the spacers to a width substantially equal to a critical dimension of conductive interconnect lines subsequently patterned in the substrate using the spacers.