Quad memory cell and method of making same

• US 7,910,407 B2
• Filed: 12/19/2008
• Issued: 03/22/2011
• Est. Priority Date: 12/19/2008
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E.
• Primary Examiner(s): Garber; Charles D
• Assistant Examiner(s): Ahmadi; Mohsen
• Application Number:
  US12/318,022
• Publication Number:
  US 20100157653A1
• Time in Patent Office: 823 Days
• Field of Search: 257/E21.053, 257/E21.18, 257/E21.602, 257/E21.613, 257/E21.614, 257/E21.645, 257/E21.658
• US Class Current: 438/128
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 2213/74 Array wherein each memory cell has more than one access device
• CPC Class Codes: G11C 2213/78 Array wherein the memory cells of a group share an access device, all the memory cells of the group having a common electrode and the access device being not part of a word line or a bit line driver
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H01L 29/1606 Graphene
• CPC Class Codes: H01L 29/868 PIN diodes
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/22 of the metal-insulator-metal type
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays

Abstract

A non-volatile memory device includes a first electrode, a diode steering element, at least three resistivity switching storage elements, and a second electrode. The diode steering element electrically contacts the first electrode and the at least three resistivity switching storage elements. The second electrode electrically contacts only one of the at least three resistivity switching storage elements.

Claims

1. A method of making a semiconductor device, comprising:

forming a conductor layer;

forming a resistivity switching storage element layer over the conductor layer;

forming at least one first layer of a diode steering element over the resistivity switching storage element layer;

patterning the conductor layer, the resistivity switching storage element layer and the at least one first layer using a first mask to form a plurality of patterns, each pattern comprising a portion of the conductor layer, a portion of the resistivity switching storage element layer and a portion of the at least one first layer;

filling spaces between adjacent patterns with a gap fill insulating material;

forming at least one second layer of the diode steering element over the patterns and over the gap fill insulating material such that the at least one second layer contacts portions of the at least one first layer in the plurality patterns; and

patterning the at least one second layer, the portions of the at least one first layer, and portions of the resistivity switching storage element layer using a second mask to form a plurality of diodes each comprising one portion of the second layer, at least three portions of the first layer separated from each other by the gap fill insulating layer and at least three resistivity switching storage elements separated from each other by the gap fill insulating layer,

wherein each of the at least three portions of the first layer contacts one of the at least three resistivity switching storage elements.

2. The method of claim 1, wherein the at least one first layer comprises a first semiconductor layer of a first conductivity type and the at least one second layer comprises a second semiconductor layer of a second conductivity type and the steps of patterning form a plurality of diode steering elements of nonvolatile memory cells.

3. The method of claim 2, wherein the at least one second layer further comprises an intrinsic layer located adjacent to the first layer of the first conductivity type.

4. The device of claim 2, wherein:

each of the plurality of diodes along with each of the respective at least three resistivity switching storage elements comprise a cell of one time programmable memory or a cell of rewritable nonvolatile memory;

each of the plurality of diodes comprises a p-n semiconductor diode, a p-i-n semiconductor diode, a metal insulator metal (MIM) diode, or a metal insulator-insulator metal (MIIM) diode; and

each resistivity switching storage element comprises a resistivity switching material selected from an antifuse dielectric, fuse, diode and antifuse dielectric arranged in a series, a polysilicon memory effect material, a metal oxide or switchable complex metal oxide material, a carbon nanotube material, a graphene switchable resistance material, a phase change material, a conductive bridge element, an electrolyte switching material, a switchable polymer material, or a carbon resistivity switching material.

5. The method of claim 1, wherein each portion of the conductor layer in each pattern electrically contacts at least three resistivity switching elements.

6. The method of claim 1, further comprising:

forming a first electrode layer;

patterning the first electrode layer;

forming a second electrode layer; and

patterning the second electrode layer,

wherein the first electrode layer is formed before the conductor layer, and the second electrode layer is formed after the at least one second layer.

7. The method of claim 6, wherein the patterned first electrode layer comprises word lines and the patterned second electrode layer comprises bit lines.

8. The method of claim 7, wherein patterning the first electrode layer includes forming bypass lines in the first electrode layer.

9. The method of claim 1, wherein the at least three resistivity switching storage elements comprise four resistivity switching storage elements.

10. The method of claim 1, wherein the at least three resistivity switching storage elements comprise three resistivity switching storage elements.