Non-volatile semiconductor storage device and method of manufacturing the same
First Claim
1. A non-volatile semiconductor storage device comprising a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series,each of the memory strings comprising:
- a first columnar semiconductor layer extending in a vertical direction to a substrate;
a charge trap layer formed to sandwich an insulation layer with the first columnar semiconductor layer and accumulating charges;
a plurality of first conductive layers formed to sandwich an insulation layer with the charge trap layer and expand in a two-dimensional manner;
a second columnar semiconductor layer formed in contact with the top surface of the first columnar semiconductor layer and extending in a vertical direction to the substrate; and
a plurality of second conductive layers formed to sandwich an insulation layer with the second columnar semiconductor layer and formed in a stripe pattern extending in a first direction orthogonal to the vertical direction;
a protection insulation layer continuously covering over the plurality of first conductive layers and the second conductive layers; and
an interlayer insulation layer formed on the protection insulation layer,respective ends of the plurality of first conductive layers in the first direction being formed in a stepwise manner in relation to each other,entirety of the plurality of the second conductive layers being formed in an area immediately above the top layer of the first conductive layers, andan etching rate of the protection insulation layer being different from an etching rate of the interlayer insulation layer.
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Accused Products
Abstract
Each of the memory strings includes: a first columnar semiconductor layer extending in a vertical direction to a substrate; a plurality of first conductive layers formed to sandwich an insulation layer with a charge trap layer and expand in a two-dimensional manner; a second columnar semiconductor layer formed in contact with the top surface of the first columnar semiconductor layer and extending in a vertical direction to the substrate; and a plurality of second conductive layers formed to sandwich an insulation layer with the second columnar semiconductor layer and formed in a stripe pattern extending in a first direction orthogonal to the vertical direction. Respective ends of the plurality of first conductive layers in the first direction are formed in a stepwise manner in relation to each other, entirety of the plurality of the second conductive layers are formed in an area immediately above the top layer of the first conductive layers, and the plurality of first conductive layers and the plurality of second conductive layers are covered with a protection insulation layer that is formed continuously with the plurality of first conductive layers and the second conductive layers.
181 Citations
20 Claims
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1. A non-volatile semiconductor storage device comprising a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series,
each of the memory strings comprising: -
a first columnar semiconductor layer extending in a vertical direction to a substrate; a charge trap layer formed to sandwich an insulation layer with the first columnar semiconductor layer and accumulating charges; a plurality of first conductive layers formed to sandwich an insulation layer with the charge trap layer and expand in a two-dimensional manner; a second columnar semiconductor layer formed in contact with the top surface of the first columnar semiconductor layer and extending in a vertical direction to the substrate; and a plurality of second conductive layers formed to sandwich an insulation layer with the second columnar semiconductor layer and formed in a stripe pattern extending in a first direction orthogonal to the vertical direction; a protection insulation layer continuously covering over the plurality of first conductive layers and the second conductive layers; and an interlayer insulation layer formed on the protection insulation layer, respective ends of the plurality of first conductive layers in the first direction being formed in a stepwise manner in relation to each other, entirety of the plurality of the second conductive layers being formed in an area immediately above the top layer of the first conductive layers, and an etching rate of the protection insulation layer being different from an etching rate of the interlayer insulation layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method of manufacturing a non-volatile semiconductor storage device having a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series, the method comprising:
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alternately laminating a plurality of first interlayer insulation layers and a plurality of first conductive layers; forming a first hole so as to penetrate the first interlayer insulation layers and the first conductive layers; forming a first columnar semiconductor layer in the first hole via a charge trap layer; alternately laminating second interlayer insulation layers and second conductive layers on the first interlayer insulation layers; forming the second interlayer insulation layers and the second conductive layers in a stripe pattern extending in a first direction orthogonal to a lamination direction; forming respective ends of the first interlayer insulation layers and respective ends of the first conductive layers in a stepwise manner in relation to each other; and covering the first interlayer insulation layers, the first conductive layers, the second interlayer insulation layers, and the second conductive layers with a protection insulation layer, in forming the respective ends in a stepwise manner, the second interlayer insulation layers and the second conductive layers are formed in such a way that the entire second interlayer insulation layers and the entire second conductive layers are formed in an area immediately above the top layer of the first conductive layers. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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Specification