Isolated-nitride-region non-volatile memory cell and fabrication method

• US 7,910,436 B2
• Filed: 06/25/2010
• Issued: 03/22/2011
• Est. Priority Date: 06/13/2005
• Status: Expired due to Fees

• Current Assignee: Microsemi SoC Corp.
• Original Assignee: Actel Corporation (Microchip Technology Incorporated)
• Inventors: McCollum, John
• Primary Examiner(s): Smith, Bradley K
• Assistant Examiner(s): Movva, Amar
• Application Number:
  US12/823,369
• Publication Number:
  US 20100261326A1
• Time in Patent Office: 270 Days
• Field of Search: 438/264, 257/E21.682
• US Class Current: 438/264
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42348 with trapping site formed by at least two separated sites, e.g. multi-particles trapping site
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

An isolated-nitride-region non-volatile memory cell is formed in a semiconductor substrate. Spaced-apart source and drain regions are disposed in the semiconductor substrate forming a channel therebetween. An insulating region is disposed over the semiconductor substrate. A gate is disposed over the insulating region and is horizontally aligned with the channel. A plurality of isolated nitride regions are disposed in the insulating region and are not in contact with either the channel or the gate.

Claims

1. A method for fabricating an isolated-nitride-region non-volatile memory cell comprising:

forming a tunnel dielectric on a semiconductor substrate;

forming a nitride layer over the tunnel dielectric to define a channel region;

forming silicon nano-crystals on the nitride layer;

selectively etching the nitride layer to form isolated nitride regions using the silicon nano-crystals as a mask;

forming a dielectric layer over the isolated nitride regions to encapsulate the isolated nitride regions;

forming a gate over the channel region; and

forming source and drain regions in the semiconductor substrate, the source and drain regions being horizontally aligned with the gate.

2. The method of claim 1, wherein forming the nitride layer comprises forming a silicon nitride layer.

3. The method of claim 1, wherein forming the nitride layer comprises forming a titanium nitride layer.

4. The method of claim 1, further including forming a layer over the tunnel dielectric prior to forming the nitride layer.

5. The method of claim 4 wherein forming a layer over the tunnel dielectric prior to forming the nitride layer comprises forming a layer of one of tungsten, titanium, silicon and germanium.