Super self-aligned trench MOSFET devices, methods, and systems

• US 7,910,439 B2
• Filed: 02/25/2009
• Issued: 03/22/2011
• Est. Priority Date: 06/11/2008
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Darwish, Mohamed N., Zeng, Jun
• Primary Examiner(s): Geyer; Scott B
• Application Number:
  US12/392,131
• Publication Number:
  US 20090309156A1
• Time in Patent Office: 755 Days
• Field of Search: None
• US Class Current: 438/270
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A manufacturing process and design structure for a super self-aligned trench power MOSFET. A plurality of super self-aligned trenches of different depths are formed into the body layer and epitaxial layers, preferably by using a multilayer stack of dielectric material etched to form spacers. Respective trenches contain gate conductors, body-contact conductors, and preferably a third trench containing a recessed field plate. This results in a MOSFET structure having high cell density and low gate charges and gate-drain charges.

Claims

1. A method of fabricating a trench transistor, comprising, in any order, the actions of:

(a) fabricating a gate trench from a first surface down toward a first-conductivity-type semiconductor drift layer, said gate trench penetrating through a second-conductivity-type body layer which overlies said drift layer;

(b) patterning a sacrificial layer to form openings above said respective gate trenches, forming respective pillars above said gate trenches, and removing said sacrificial layer;

(c) forming sidewall spacers on said pillar;

(d) fabricating a body-contact trench from said first surface into said body layer, in locations where said body layer is not covered by said sidewall spacers nor by said pillars; and

(e) introducing an additional dopant concentration of said second-conductivity type, in addition to the doping of said body layer, into the region surrounding the bottom of said body-contact trench;

whereby said steps (a) and (b) form said gate trench and said body-contact trench in a mutually self-aligned spatial relationship.

2. The method of claim 1, wherein the step of fabricating said body contact trench is performed by forming a first dielectric material which extends upward from said gate trench, and forming filaments of a second dielectric material on sidewalls of said first dielectric material.

3. The method of claim 2, wherein said first and second dielectric materials are the same.

4. The method of claim 1, wherein said first conductivity-type is n-type, and said second conductivity-type is p-type.

5. The method of claim 1, wherein said gate trench also penetrates a first-conductivity-type source layer which overlies said body layer.

6. The method of claim 1, wherein said gate trench also penetrates a first-conductivity-type source region which overlies said body layer, and wherein said body-contact trench contains conductive material that is also in contact with said source region.

7. The method of claim 1, wherein said additional dopant concentration region extends onto a junction formed between said body layer and said drift layer.

8. The method of claim 1, wherein said gate trench and said body-contact trench have different depths.

9. A method of fabricating a trench gate semiconductor field-effect transistor, comprising, in any order, the actions of:

fabricating a gate trench, through a first-conductivity-type source region and a second-conductivity-type body layer, toward a first-conductivity-type semiconductor drift layer; and

forming a gate conductor, in said gate trench, which is capacitively coupled to at least part of said body layer; and

also patterning a sacrificial layer to form openings above said respective gate trenches, forming respective pillars above said gate trenches, and removing said sacrificial layer;

forming respective sidewall spacers on ones of said pillars;

etching a body-contact trench into said body layer;

depositing conductive material into said body-contact trench to form a contact to said body layer;

wherein said gate trench and said body-contact trench are formed in a mutually self-aligned spatial relationship.

10. The method of claim 9, wherein said gate conductor comprises polysilicon.

11. The method of claim 9, wherein said contact to said body layer also makes contact to said source region.

12. The method of claim 9, wherein a dielectric layer is grown on sidewalls of said gate trench before said gate conductor is formed.

13. The method of claim 9, wherein said body contact trench is formed by forming a first dielectric material which extends upward from said gate trench, and forming filaments of a second dielectric material on sidewalls of said first dielectric material.

14. The method of claim 13, wherein said first and second dielectric materials are the same.

15. A method of fabricating a super self-aligned trench gate transistor, comprising, in any order, the actions of:

a) fabricating a gate trench and a recessed field plate (RFP) trench from a first surface down toward a semiconductor drift layer of a first-conductivity-type material;

said gate trench and recessed field plate trench spanning a second-conductivity-type body layer which overlies at least some parts of said drift layer; and

, within said gate trench and said recessed field plate trench respectively, forming a gate conductor and a recessed field plate conductor respectively;

b) fabricating a body-contact trench from said first surface into said body layer;

and depositing conductive material into said body-contact trenches to form contact conductors which connect to said body layer; and

c) fabricating a source electrode over the surface of said gate conductors and contact conductors, wherein said steps (a) and (b) form said gate trench and said body-contact trench in a mutually self-aligned spatial relationship.

16. The method of claim 15, wherein the step of fabricating said body contact trench is performed by forming a first dielectric material which extends upward from said gate trench, and forming filaments of a second dielectric material on sidewalls of said first dielectric material.

17. The method of claim 16, wherein said first and second dielectric materials are the same.

18. The method of claim 15, wherein said gate trench, the RFP trench and said body-contact trench are all of different depths.

19. The method of claim 15, wherein said gate trench has a step-shaped oxide.

20. The method of claim 15, wherein said gate trench is lined with dielectric, which is thicker at the bottom of said gate trench.