System and method for providing a self aligned bipolar transistor using a simplified sacrificial nitride emitter
First Claim
1. A method of manufacturing a self aligned bipolar transistor comprising the steps of:
- forming an active region of the transistor;
forming a silicon nitride sacrificial emitter above the active region of the transistor;
depositing a physical vapor deposition oxide layer over the silicon nitride sacrificial emitter using a physical vapor deposition process;
exposing a top of the silicon nitride sacrificial emitter without performing a chemical mechanical polishing process;
performing a hot phosphoric acid etch process to remove the silicon nitride sacrificial emitter and create an emitter window;
depositing an oxide spacer layer over vertical side walls and a bottom of the emitter window;
forming polysilicon spacers over vertical side walls and portions of a bottom of the oxide spacer layer in the emitter window; and
performing a second etch process to remove a portion of the bottom of the oxide spacer layer that is not covered by the polysilicon spacers to expose an underlying base portion of the transistor.
1 Assignment
0 Petitions
Accused Products
Abstract
A system and method are disclosed for providing a self aligned bipolar transistor using a simplified sacrificial nitride emitter. An active region of a transistor is formed and a silicon nitride sacrificial emitter is formed above the active region of the transistor. Then a physical vapor deposition oxide layer is deposited over the silicon nitride sacrificial emitter using a physical vapor deposition process. The physical vapor deposition oxide layer is then etched away from the side walls of the sacrificial emitter. The sacrificial emitter is then etched away to form an emitter window. Then a polysilicon emitter structure is formed in the emitter window. The self aligned bipolar transistor architecture of the invention is compatible with BiCMOS technology.
-
Citations
20 Claims
-
1. A method of manufacturing a self aligned bipolar transistor comprising the steps of:
-
forming an active region of the transistor; forming a silicon nitride sacrificial emitter above the active region of the transistor; depositing a physical vapor deposition oxide layer over the silicon nitride sacrificial emitter using a physical vapor deposition process; exposing a top of the silicon nitride sacrificial emitter without performing a chemical mechanical polishing process; performing a hot phosphoric acid etch process to remove the silicon nitride sacrificial emitter and create an emitter window; depositing an oxide spacer layer over vertical side walls and a bottom of the emitter window; forming polysilicon spacers over vertical side walls and portions of a bottom of the oxide spacer layer in the emitter window; and performing a second etch process to remove a portion of the bottom of the oxide spacer layer that is not covered by the polysilicon spacers to expose an underlying base portion of the transistor. - View Dependent Claims (2, 3, 4, 5, 6)
-
-
7. A method of manufacturing a self aligned bipolar transistor comprising the steps of:
-
forming an active region of the transistor that comprises a collector portion covered by a base portion covered by a silicon oxide material; forming a silicon nitride sacrificial emitter on the silicon oxide material above the active region of the transistor; removing portions of the silicon oxide material that are not under the silicon nitride sacrificial emitter; growing an in-situ layer of silicon/polysilicon on an external base region of the base portion of the transistor; depositing a physical vapor deposition oxide layer over the silicon nitride sacrificial emitter and over the layer of silicon/polysilicon using a physical vapor deposition process; exposing a top of the silicon nitride sacrificial emitter without performing a chemical mechanical polishing process; performing a hot phosphoric acid etch process to remove the silicon nitride sacrificial emitter and create an emitter window; depositing an oxide spacer layer over vertical side walls and a bottom of the emitter window; forming polysilicon spacers over vertical side walls and portions of a bottom of the oxide spacer layer in the emitter window; and performing a second etch process to remove a portion of the bottom of the oxide spacer layer that is not covered by the polysilicon spacers to expose the underlying base portion of the transistor. - View Dependent Claims (8, 9, 10, 11, 12, 13)
-
-
14. A method of manufacturing a self aligned bipolar transistor comprising the steps of:
-
forming an active region of the transistor that comprises a collector portion covered by a base portion covered by a silicon oxide material; forming a silicon nitride sacrificial emitter on the silicon oxide material above the active region of the transistor; removing portions of the silicon oxide material that are not under the silicon nitride sacrificial emitter; performing a self aligned base implantation process on an external base region of the base portion of the transistor; depositing a physical vapor deposition oxide layer over the silicon nitride sacrificial emitter using a physical vapor deposition process; exposing a top of the silicon nitride sacrificial emitter without performing a chemical mechanical polishing process; performing a hot phosphoric acid etch process to remove the silicon nitride sacrificial emitter and create an emitter window; depositing an oxide spacer layer over vertical side walls and a bottom of the emitter window; forming polysilicon spacers over vertical side walls and portions of a bottom of the oxide spacer layer in the emitter window; and performing a second etch process to remove a portion of the bottom of the oxide spacer layer that is not covered by the polysilicon spacers to expose the underlying base portion of the transistor. - View Dependent Claims (15, 16, 17, 18, 19, 20)
-
Specification