Storage nitride encapsulation for non-planar sonos NAND flash charge retention

• US 7,910,453 B2
• Filed: 07/14/2008
• Issued: 03/22/2011
• Est. Priority Date: 07/14/2008
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Chun-Pei, Xu, Jeff J., Hsieh, Chia-Ta, Lee, Chun-Hung
• Primary Examiner(s): Richards; N Drew
• Assistant Examiner(s): Garcia; Joannie A
• Application Number:
  US12/172,687
• Publication Number:
  US 20100006974A1
• Time in Patent Office: 981 Days
• Field of Search: 438/196, 438/218, 438/221, 438/294, 438/296, 438/404, 438/412, 438/FOR.221, 438/424, 257/93, 257/374, 257/446, 257/501, 257/506, 257/E21.54, 257/E21.545, 257/E21.564
• US Class Current: 438/424
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

The present disclosure provides a method of manufacturing a microelectronic device. The method includes forming recessed shallow trench isolation (STI) features in a semiconductor substrate, defining a semiconductor region between adjacent two of the recessed STI features; forming a tunnel dielectric feature within the semiconductor region; forming a nitride layer on the recessed STI features and the tunnel dielectric feature; etching the nitride layer to form nitride openings within the recessed STI features; partially removing the recessed STI features through the nitride openings, resulting in gaps between the nitride layer and the recessed STI features; and forming a first dielectric material on surfaces of the nitride layer, sealing the nitride openings.

Claims

1. A method of manufacturing a microelectronic device, comprising:

forming recessed shallow trench isolation (STI) features in a semiconductor substrate, defining a semiconductor region between adjacent two of the recessed STI features;

forming a tunnel dielectric feature within the semiconductor region;

forming a nitride layer on the recessed STI features and the tunnel dielectric feature;

etching the nitride layer to form nitride openings within the recessed STI features;

partially removing the recessed STI features through the nitride openings, resulting in gaps between the nitride layer and the recessed STI features; and

forming a first dielectric material on surfaces of the nitride layer, sealing the nitride openings.

2. The method of claim 1, further comprising:

forming a thin dielectric layer on the surfaces of the nitride layer and sidewalls of the semiconductor substrate after partially removing the recessed STI features and before forming the first dielectric material.

3. The method of claim 2, wherein forming the thin dielectric material comprises forming a thin silicon oxide layer using radical oxidation.

4. The method of claim 1, wherein forming the recessed STI features comprises:

forming trenches in the semiconductor substrate; and

filling the trenches with a second dielectric material by chemical vapor deposition (CVD).

5. The method of claim 4, wherein filling the trenches with the second dielectric material comprises forming silicon oxide by high density plasma chemical vapor deposition (HDPCVD).

6. The method of claim 1, wherein the tunnel dielectric feature comprises silicon oxide.

7. The method of claim 1, wherein forming the nitride layer comprises forming a silicon-rich silicon nitride layer.

8. The method of claim 1, wherein etching the nitride layer comprises:

forming a non-conformal polymeric material layer on the nitride layer as a self-aligned mask;

applying plasma dry etch to cut through the nitride layer on the recessed STI features; and

removing the non-conformal polymeric material layer.

9. The method of claim 1, wherein partially removing the recessed isolation features comprises applying a wet etching to the recessed STI features through the nitride openings.

10. The method of claim 1, wherein forming the first dielectric material comprises growing a high temperature oxide (HTO).

11. A method of manufacturing a microelectronic device, comprising:

providing a silicon substrate having a recessed trench isolation feature in a dielectric region and a silicon feature in a silicon region adjacent the dielectric region;

forming a tunnel dielectric feature on the silicon substrate within the silicon region;

forming a silicon-rich nitride layer on a silicon substrate;

etching the silicon-rich nitride layer to form an opening within the dielectric region;

etching the recessed trench isolation feature through the opening to form a gap between the silicon-rich nitride layer and the recessed trench isolation feature; and

forming a first dielectric material on the silicon-rich nitride layer and sidewalls of the silicon feature.

12. The method of claim 11, wherein the forming of the first dielectric material comprises:

forming a thin silicon oxide layer using radical oxidation; and

growing a high temperature oxide (HTO) layer on the thin silicon oxide layer.

13. The method of claim 11, wherein the forming of the tunnel dielectric feature comprises forming a silicon oxide layer on the silicon feature.

14. A semiconductor device comprising:

a recessed shallow trench isolation (STI) feature formed in a semiconductor substrate, defining a STI region and a semiconductor region;

a tunnel oxide feature disposed on the semiconductor substrate within the semiconductor region;

a silicon nitride layer disposed on the semiconductor substrate, overlying the tunnel oxide feature and the recessed STI feature; and

a silicon oxide layer within the STI region and interposed between the recessed STI feature and the silicon nitride layer, separating the silicon nitride layer from sidewall of the semiconductor substrate.

15. The semiconductor device of claim 14, wherein the silicon oxide layer is disposed defining a void between the silicon oxide layer and one of the isolation features.

16. The semiconductor device of claim 14, wherein the silicon nitride comprises conductive silicon-rich nitride.

17. The semiconductor device of claim 14, further comprising a dielectric feature disposed on the silicon nitride layer, wherein the dielectric feature includes one of silicon oxide and aluminum oxide.

18. The semiconductor device of claim 14, wherein the semiconductor device comprises a FINFET-like memory cell.