Method for forming nanotube semiconductor devices

• US 7,910,486 B2
• Filed: 06/12/2009
• Issued: 03/22/2011
• Est. Priority Date: 06/12/2009
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Inc. (Alpha & Omega Semiconductor, Ltd.)
• Original Assignee: Alpha & Omega Semiconductor, Inc. (Alpha & Omega Semiconductor, Ltd.)
• Inventors: Wang, Xiaobin, Bhalla, Anup, Chen, John, Yilmaz, Hamza, Chang, Hong
• Primary Examiner(s): Nhu; David
• Application Number:
  US12/484,166
• Publication Number:
  US 20100317158A1
• Time in Patent Office: 648 Days
• Field of Search: 438/197, 438/363, 438/389, 438/429, 438/505, 438/508, 438/510, 438/222, 438/246, 438/692, 438/700, 257/E21.042, 257/E21.043, 257/E21.051, 257/E21.077, 257/E21.267, 257/E21.404, 257/E21.435, 257/E21.545, 257/E21.546, 257/E21.562
• US Class Current: 438/700
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/6609 Diodes
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate. A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure.

Claims

1. A method for forming a semiconductor device, the method comprising:

forming a plurality of trenches in a top surface of a first semiconductor layer of a first conductivity type, the trenches forming mesas in the first semiconductor layer;

forming by epitaxial growth a first epitaxial layer of a second conductivity type on the top surface of the first semiconductor layer covering at least sidewalls of the trenches;

forming a first dielectric layer in the trenches, the first dielectric layer filling at least part of the trenches;

forming a gate dielectric layer on the sidewalls of at least a first trench above the first dielectric layer and adjacent to the first epitaxial layer;

forming a gate conductive layer in the first trench, the gate conductive layer being formed above the first dielectric layer and adjacent the gate dielectric layer; and

providing a second semiconductor layer of the second conductivity type located at a bottom surface of the first semiconductor layer, the first epitaxial layer being electrically connected to the second semiconductor layer,

wherein the first epitaxial layer is disposed along the sidewalls of the trenches and has uniform doping concentration, the first epitaxial layer having a first thickness and a first doping concentration and a mesa of the first semiconductor layer having a second thickness in a horizontal dimension and a second doping concentration, the first and second thicknesses and the first and second doping concentrations being selected to achieve charge balance in operation.

2. The method of claim 1 wherein the second semiconductor layer of the second conductivity type comprises a heavily doped semiconductor substrate of the second conductivity type, and wherein prior to forming a plurality of trenches, the method further comprises:

providing the heavily doped semiconductor substrate of the second conductivity type; and

forming the first semiconductor layer of the first conductivity type on a top surface of the semiconductor substrate.

3. The method of claim 1, wherein the first semiconductor layer of the first conductivity type is a lightly doped semiconductor substrate, and wherein after forming the gate conductive layer, the method further comprises:

grinding a backside of the lightly doped semiconductor substrate to remove the semiconductor substrate approximately up to a bottom surface of the dielectric-filled trenches; and

forming the second semiconductor layer of the second conductivity type on the newly exposed backside of the lightly doped semiconductor substrate, the second semiconductor layer being heavily doped.

4. The method of claim 3, wherein forming the heavily doped second semiconductor layer comprises performing an implantation of the second conductivity type on the newly exposed backside of the lightly doped semiconductor substrate.

5. The method of claim 3, wherein grinding the backside of the lightly doped semiconductor substrate further comprises grinding a backside of the semiconductor substrate to remove the semiconductor substrate up to a bottom surface of the first dielectric layer.

6. The method of claim 3, wherein forming the heavily doped second semiconductor layer of the second conductivity type comprises epitaxially growing the heavily doped second semiconductor layer of the second conductivity type on the newly exposed backside of the lightly doped semiconductor substrate.

7. The method of claim 6, wherein grinding the backside of the lightly doped semiconductor substrate removes the semiconductor substrate up to a first distance away from a bottom surface of the dielectric-filled trench.

8. The method of claim 1, further comprising:

before forming the first dielectric layer in the trenches, performing an anisotropic ion implantation of the second conductivity type, the anisotropic ion implantation forming doped regions of the second conductivity type at bottoms of the trenches.

9. The method of claim 1, further comprising:

forming a body region of the first conductivity type in a top portion of at least a first mesa of the first semiconductor layer, the body region extending to a depth near a bottom edge of the gate conductive layer formed in the first trench;

forming a heavily doped source region of the second conductivity type in the body region adjacent to the sidewall of the first trench, the source region extending to a depth near a top edge of the gate conductive layer; and

wherein a vertical trench MOSFET is formed with the second semiconductor layer being a drain region, the first epitaxial layer being a drain drift region, and the gate conductive layer being a gate electrode of the vertical trench MOSFET.

10. The method of claim 9, further comprising:

forming a second dielectric layer over the gate conductive layer and the first semiconductor layer;

forming an opening in the second dielectric layer on the top surface of the first semiconductor layer; and

forming a source electrode in the opening to contact the source region and the body region.

11. The method of claim 1, wherein forming by epitaxial growth a first epitaxial layer of the second conductivity type comprises forming by epitaxial growth a first epitaxial layer of the second conductivity type having a thickness of equal to or less than 200 nm.

12. The method of claim 1, wherein forming a first dielectric layer in the trenches comprises:

depositing an oxide layer in the trenches, the deposited oxide layer filling up the trenches and covering the mesas of the first semiconductor layer; and

etching the deposited oxide layer until the oxide layer only fills part of the trenches.

13. The method of claim 1, wherein the first semiconductor layer is more lightly doped than the first epitaxial layer.

14. The method of claim 1, wherein a product of the first thickness and the first doping concentration of the first epitaxial layer is about equal to one half of a product of the second thickness and the second doping concentration of the mesas of the first semiconductor layer, the second thickness being a horizontal dimension of a mesa of the first semiconductor layer.

15. The method of claim 1, wherein prior to forming by epitaxial growth a first epitaxial layer of the second conductivity type, the method further comprises:

forming by epitaxial growth a second epitaxial layer of the first conductivity type on the first semiconductor layer, the second epitaxial layer covering the sidewalls of the trenches;

wherein forming by epitaxial growth the first epitaxial layer comprising forming by epitaxial growth the first epitaxial layer of the second conductivity type on the second epitaxial layer,

wherein the first epitaxial layer and the second epitaxial layer form parallel doped regions along the sidewalls of the trenches, the first epitaxial layer and the second epitaxial layer each having uniform doping concentration, the first epitaxial layer having the first thickness and the first doping concentration and the second epitaxial layer and a mesa of the first semiconductor layer together having a third thickness and a third average doping concentration, the first and third thicknesses and the first doping concentration and third average doping concentrations being selected to achieve charge balance in operation.

16. The method of claim 15, wherein the second semiconductor layer of the second conductivity type comprises a heavily doped semiconductor substrate of the second conductivity type, and wherein prior to forming a plurality of trenches, the method further comprises:

providing the heavily doped semiconductor substrate of the second conductivity type; and

forming the first semiconductor layer of the first conductivity type on a top surface of the semiconductor substrate,

wherein the first epitaxial layer formed on the second epitaxial layer is electrically connected to the semiconductor substrate through out-diffusion of dopants from the semiconductor substrate.

17. The method of claim 15, wherein the second epitaxial layer is more heavily doped than the first semiconductor layer.

18. The method of claim 15, wherein a product of the first thickness and the first doping concentration of the first epitaxial layer is about equal to one half of a product of the third thickness and the third average doping concentration of the second epitaxial layer and the mesa of the first semiconductor layer.

19. The method of claim 1, wherein the first conductivity type comprises N-type conductivity and the second conductivity type comprises P-type conductivity.

20. The method of claim 1, wherein the first conductivity type comprises P-type conductivity and the second conductivity type comprises N-type conductivity.

21. The method of claim 1, wherein the steps are carried out at a temperature of 1000°

C. or below after the epitaxial process.

22. The method of claim 15, wherein bottom regions of the trenches are counterdoped such that the first epitaxial layer is electrically connected with the second semiconductor layer.

23. The method of claim 1, further comprising:

forming a body region of the first conductivity type in a top portion of at least a first mesa of the first semiconductor layer, the body region extending to a depth near a bottom edge of the gate conductive layer formed in the first trench;

forming a heavily doped source region of the second conductivity type in the body region adjacent to the sidewall of the first trench, the source region extending to a depth near a top edge of the gate conductive layer;

forming a source electrode on the top surface to electrically contact the source region and the body region;

forming an internal emitter layer of the first conductivity on the bottom surface of the second semiconductor layer; and

forming a collector electrode on the bottom surface in contact with the internal emitter layer,

wherein an insulated gate bipolar transistor (IGBT) is formed with the second semiconductor layer being a buffer or field stop region, the body region being an internal collector region, the source electrode being an emitter electrode, and the gate conductive layer being a gate electrode of the IGBT.

24. The method of claim 1, further comprising:

forming an anode contact region of the first conductivity type in a second mesa of the first semiconductor layer, the second mesa being adjacent to trenches filled with the first dielectric layer with or without the gate conductive layer; and

forming a Schottky metal layer on the top surface of the second mesa and the first epitaxial layer and the anode contact region, the Schottky metal being in contact with the first epitaxial layer to form a Schottky junction,

wherein a Schottky diode is formed with the second semiconductor layer being a cathode terminal and the Schottky metal layer being an anode terminal.

25. The method of claim 24 further comprising:

performing a shallow implant of the first conductivity type in the first epitaxial layer to adjust the Schottky barrier height of the first epitaxial layer.

26. The method of claim 1, further comprising:

forming an anode contact region of the first conductivity type in a third mesa of the first semiconductor layer and extending to the first epitaxial layer formed on the sidewalls of the third mesa, the third mesa being adjacent to trenches filled with the first dielectric layer with or without the gate conductive layer, a P-N junction being formed between the anode contact region and the first epitaxial layer; and

forming an ohmic metal layer on the top surface of the third mesa in electrical contact with the anode contact region,

wherein a P-N junction diode is formed with the second semiconductor layer being a cathode terminal and the ohmic metal layer being an anode terminal.