Semiconductor device

• US 7,910,923 B2
• Filed: 12/20/2007
• Issued: 03/22/2011
• Est. Priority Date: 12/22/2006
• Status: Active Grant

• Current Assignee: Nissan Motor Co., Ltd.
• Original Assignee: Nissan Motor Co., Ltd.
• Inventors: Tanaka, Hideaki, Hoshi, Masakatsu, Hayashi, Tetsuya, Yamagami, Shigeharu
• Primary Examiner(s): Jackson, Jr.; Jerome
• Assistant Examiner(s): PAGE, DALE E
• Application Number:
  US11/961,221
• Publication Number:
  US 20080210938A1
• Time in Patent Office: 1,188 Days
• Field of Search: 257/472, 257/109, 257/121, 257/212, 257/51, 257/64, 257/E29.292
• US Class Current: 257/51
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

A semiconductor device with superior long-term reliability is disclosed that alleviates current concentration into a switch structure arranged at an outermost portion. The semiconductor device comprises hetero semiconductor regions formed of polycrystalline silicon having a band gap width different from that of a drift region and hetero-adjoined with the drift region, a gate insulation film, a gate electrode adjoined to the gate insulation film, a source electrode connected to a source contact portion of the hetero semiconductor regions and an outermost switch structure and a repeating portion switch structure with a drain electrode connected to a substrate region. In a conduction state, the outermost switch structure comprises a mechanism in which the current flowing at the outermost switch structure becomes smaller than the current flowing at the repeating portion switch structure.

Claims

1. A semiconductor device, comprising:

a plurality of inner switch structures arranged in parallel and integrated in an inner portion on one semiconductor chip, each switch structure including;

a semiconductor substrate formed from a first semiconductor material;

a hetero semiconductor region formed from a second semiconductor material having a band gap width different from that of the first semiconductor material, the hetero semiconductor region being hetero-adjoined with the semiconductor substrate;

a gate insulation film adjoined to a heterojunction of the semiconductor substrate and the hetero semiconductor region;

a gate electrode adjoined to the gate insulation film;

a source electrode connected to a source contact portion of the hetero semiconductor region; and

a drain electrode connected to the semiconductor substrate; and

an outer switch structure arranged at an outermost portion of the semiconductor chip and not forming one of the plurality of inner switch structures, the outer switch structure including;

an outer hetero semiconductor region formed of a third semiconductor material having different conductive-type impurities than the second semiconductor material and hetero-adjoined with the semiconductor substrate;

an outer gate insulation film adjoined to a heterojunction of the semiconductor substrate and the outer hetero semiconductor region; and

an outer gate electrode adjoined to the outer gate insulation film;

wherein the source electrode of one of the plurality of inner switch structures is connected to a source contact portion of the outer hetero semiconductor region; and

wherein the outer switch structure is a current-resistant structure configured to reduce current flowing at the outer switch structure when the inner switch structures are conducting the current.

2. The semiconductor device according to claim 1 wherein a first hetero barrier height of the outer hetero semiconductor region is higher than a second hetero barrier height of the hetero semiconductor regions of the inner switch structures.

3. The semiconductor device according to claim 2 wherein a conductive type of the outer hetero semiconductor region differs from a conductive type of the semiconductor substrate.

4. The semiconductor device according to claim 1, wherein a heterojunction driving end is a region where a respective heterojunction between hetero semiconductor regions and the semiconductor substrate is adjoined to a respective gate insulation film, and wherein the outer switch structure has a resistance from its heterojunction driving end to its source contact portion greater than a resistance from a source contact portion of an inner switch structure to its heterojunction driving end.

5. The semiconductor device according to claim 4 wherein an impurity concentration of the outer hetero semiconductor region is less than an impurity concentration of the hetero semiconductor regions of the inner switch structures.

6. The semiconductor device according to claim 1, wherein a heterojunction driving end is a region where a respective heterojunction between hetero semiconductor regions and the semiconductor substrate is adjoined to a respective gate insulation film, and wherein the outer switch structure comprises an outermost electric field alleviating region adjoined to its heterojunction driving end and the inner switch structures comprise an electric field alleviating region in areas adjoined to the semiconductor substrate and one of the hetero semiconductor region or the gate insulation film.

7. The semiconductor device according to claim 6 wherein a gate electric field strength of the heterojunction driving end of the outer switch structure is less than a gate electric field strength of the heterojunction driving end of the inner switch structures when in a conduction state.

8. The semiconductor device according to claim 6 wherein a drain electric field strength of the heterojunction driving end of the outer switch structure is less than a drain electric field strength of the heterojunction driving end of the inner switch structures when in an interruption state.

9. The semiconductor device according to claim 1 wherein an angle between the heterojunction of the semiconductor substrate and the outer hetero semiconductor region and the outer gate insulation film is greater than an angle between a respective heterojunction and gate insulation film of the inner switch structures.

10. The semiconductor device according to claim 9 wherein a heterojunction driving end is a region where a respective heterojunction between hetero semiconductor regions and the semiconductor substrate is adjoined to a respective gate insulation film and wherein a drain electric field strength of a heterojunction driving end of the outer switch structure is less than a drain electric field strength of heterojunction driving ends of the inner switch structures when in an interruption state.

11. The semiconductor device according to claim 9 wherein a hetero barrier height of the outer hetero semiconductor region is greater than a hetero barrier height of the hetero semiconductor region of each inner switch structure.

12. The semiconductor device according to claim 11 wherein a conductive type of the outer hetero semiconductor region differs from a conductive type of the semiconductor substrate.

13. The semiconductor device according to claim 9 wherein a heterojunction driving end is a region where a respective heterojunction between hetero semiconductor regions and the semiconductor substrate is adjoined to a respective gate insulation film, and wherein a resistance from a heterojunction driving end of the outer switch structure to the source contact portion of the outer switch structure is greater than a resistance from a heterojunction driving end of each inner switch structure to the source contact portion of each inner switch structure.

14. The semiconductor device according to claim 13 wherein an impurity concentration of the outer hetero semiconductor region is less than an impurity concentration of the hetero semiconductor regions of the inner switch structures.

15. The semiconductor device according to claim 9, wherein a heterojunction driving end is a region where a respective heterojunction between hetero semiconductor regions and the semiconductor substrate is adjoined to a respective gate insulation film and further comprising:

an outermost electric field alleviating region adjoined to a heterojunction driving end of the outer switch structure and not adjoined to heterojunction driving ends of the inner switch structures.

16. The semiconductor device according to claim 15 wherein a gate electric field strength of the heterojunction driving end of the outer switch structure is less than a respective gate electric field strength of the heterojunction driving ends of the inner switch structures when in a conduction state.

17. The semiconductor device according to claim 15 wherein a drain electric field strength of the heterojunction driving end of the outer switch structure is less than a respective drain electric field strength of the heterojunction driving ends of the inner switch structures when in an interruption state.

18. The semiconductor device according to claim 1 wherein the first semiconductor material is formed from at least one of silicon carbide, diamond, and gallium nitride.

19. The semiconductor device according to claim 1 wherein the second semiconductor material is formed from at least one of a single crystal silicon, a polycrystalline silicon, and an amorphous silicon.