Semiconductor device and method for fabricating the same

• US 7,910,985 B2
• Filed: 04/14/2010
• Issued: 03/22/2011
• Est. Priority Date: 06/28/2000
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Ooishi, Kentaro, Inagawa, Hiroshi, Machida, Nobuo
• Primary Examiner(s): Tsai; H. Jey
• Application Number:
  US12/759,858
• Publication Number:
  US 20100193863A1
• Time in Patent Office: 342 Days
• Field of Search: 257328-345, 257/E21.418
• US Class Current: 257/328
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0611 for increasing or controlling the breakdown voltage of reverse biased devices H01L29/0661 takes precedence
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7804 the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.

Claims

1. A semiconductor device including

a semiconductor substrate,

a first insulating film formed in the semiconductor substrate and having a rectangular ring form,

a MISFET formed within a region of the semiconductor substrate surrounded by the first insulating film,

a well region of a first conductivity type formed in the semiconductor substrate and arranged below the first insulating film and along the rectangular ring form,

the MISFET comprising:

a semiconductor layer of a second conductivity type opposite to the first conductivity type formed in the semiconductor substrate, which serves as a drain region;

a base region of the first conductivity type formed in the semiconductor substrate such that the base region is formed in the semiconductor substrate, in which a channel is to be formed;

a source region of the second conductivity type formed in the semiconductor substrate such that the source region is formed over the base region, which has a pair of side surfaces opposite each other and an upper surface;

a trench formed in the semiconductor substrate, which has contacts with the semiconductor layer, the base region and the source region;

a gate insulating film formed inside the trench;

a gate electrode formed over the gate insulating film and inside the trench;

a second insulating film formed over the gate electrode and the upper surface of the source region;

a contact hole formed in the second insulating film and the semiconductor substrate, whose bottom is located lower than the upper surface of the source region, the contact hole having contacts with the source region and the base region; and

a source wiring formed in the contact hole electrically connected with the source region and the base region,

wherein the source wiring has contacts with the upper surface of the source region and the side surface of the source region, and

wherein the trench and the gate electrode extend in the well region such that a termination portion of the gate electrode extends over the first insulating film to extend a depletion layer below the first insulating film.

2. The semiconductor device according to claim 1, wherein the semiconductor layer is a silicon layer and the second insulating film is a silicon oxide film.

3. The semiconductor device according to claim 1, wherein the semiconductor layer is a single crystal silicon layer.

4. The semiconductor device according to claim 1, wherein each of the semiconductor layer and the source region is made of an n type semiconductor, and the base region is made of a p type semiconductor.

5. The semiconductor device according to claim 1, wherein the gate electrode has a mesh structure in plan view, and the gate electrodes are disposed in a lattice form.

6. The semiconductor device according to claim 1, wherein a drain electrode is formed over a back surface of the semiconductor substrate, and the drain electrode and the drain region are electrically connected.

7. The semiconductor device according to claim 1, wherein a contact layer is formed in the base region;

the contact layer and the base region have a same conduction type;

an impurity concentration of the contact layer is greater than that of the base region; and

the lower portion of the contact hole and the contact layer are contacted.

8. The semiconductor device according to claim 1, wherein the well region functions as a field relaxing portion for relaxing the electric field at the termination portion of the gate electrode.

9. The semiconductor device according to claim 1, wherein the well region has an impurity concentration different from an impurity concentration of the base region.

10. The semiconductor device according to claim 9, wherein the well region functions as a field relaxing portion for relaxing the electric field at the termination portion of the gate electrode.

11. The semiconductor device according to claim 1, wherein the well region has a depth, in the substrate, different from the depth of the base region.

12. The semiconductor device according to claim 11, wherein the well region functions as a field relaxing portion for relaxing the electric field at the termination portion of the gate electrode.