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Method for four direction low capacitance ESD protection

  • US 7,910,999 B2
  • Filed: 12/23/2008
  • Issued: 03/22/2011
  • Est. Priority Date: 07/29/2002
  • Status: Active Grant
First Claim
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1. A low capacitance device structure with associated parasitic bipolar transistors on a substrate for the purpose of providing four-way electrostatic voltage discharge protection to the active semiconductor devices connected to the I/O logic circuit line and including ESD protection of the power bus system comprising:

  • a first doped region with contact area of opposite dopant than said substrate;

    isolation elements within said substrate;

    a first FET gate element upon said substrate surface;

    a second doped region within said first doped region of opposite dopant than said first doped region;

    a third doped region within said substrate of opposite dopant than said substrate;

    a fourth doped region within said substrate of opposite dopant than said substrate;

    a fifth doped region within said substrate of opposite dopant than said substrate;

    a sixth doped region within said substrate of opposite dopant than said substrate;

    a seventh doped region within said substrate of similar dopant to said substrate;

    an eighth doped region within said substrate of similar dopant to said substrate;

    an electrical connection system for said plurality of doped region and said FET gate;

    a surface passivation layer for said ESD protection device,wherein said third doped region forms an N+ guard ring around an SCR device and said fourth doped region forms said SCR cathode and said fifth doped region forms a source region and said sixth doped region forms a drain region, and said source and drain regions adjacent to said first FET gate element to form an NFET device.

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