Method for four direction low capacitance ESD protection
First Claim
1. A low capacitance device structure with associated parasitic bipolar transistors on a substrate for the purpose of providing four-way electrostatic voltage discharge protection to the active semiconductor devices connected to the I/O logic circuit line and including ESD protection of the power bus system comprising:
- a first doped region with contact area of opposite dopant than said substrate;
isolation elements within said substrate;
a first FET gate element upon said substrate surface;
a second doped region within said first doped region of opposite dopant than said first doped region;
a third doped region within said substrate of opposite dopant than said substrate;
a fourth doped region within said substrate of opposite dopant than said substrate;
a fifth doped region within said substrate of opposite dopant than said substrate;
a sixth doped region within said substrate of opposite dopant than said substrate;
a seventh doped region within said substrate of similar dopant to said substrate;
an eighth doped region within said substrate of similar dopant to said substrate;
an electrical connection system for said plurality of doped region and said FET gate;
a surface passivation layer for said ESD protection device,wherein said third doped region forms an N+ guard ring around an SCR device and said fourth doped region forms said SCR cathode and said fifth doped region forms a source region and said sixth doped region forms a drain region, and said source and drain regions adjacent to said first FET gate element to form an NFET device.
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Abstract
The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of heavily doped P+ guard rings surrounding the I/O ESD protection device and the Vcc to Bss protection device. In addition, there is a heavily doped N+ guard ring surrounding the I/O protection device its P+ guard ring. The guard rings enhance structure diode elements providing enhanced ESD energy discharge path capability enabling the elimination of a specific conventional Vss to I/O pad ESD protection device. This reduces the capacitance seen by the I/O circuit while still providing adequate ESD protection for the active circuit devices.
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Citations
14 Claims
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1. A low capacitance device structure with associated parasitic bipolar transistors on a substrate for the purpose of providing four-way electrostatic voltage discharge protection to the active semiconductor devices connected to the I/O logic circuit line and including ESD protection of the power bus system comprising:
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a first doped region with contact area of opposite dopant than said substrate; isolation elements within said substrate; a first FET gate element upon said substrate surface; a second doped region within said first doped region of opposite dopant than said first doped region; a third doped region within said substrate of opposite dopant than said substrate; a fourth doped region within said substrate of opposite dopant than said substrate; a fifth doped region within said substrate of opposite dopant than said substrate; a sixth doped region within said substrate of opposite dopant than said substrate; a seventh doped region within said substrate of similar dopant to said substrate; an eighth doped region within said substrate of similar dopant to said substrate; an electrical connection system for said plurality of doped region and said FET gate; a surface passivation layer for said ESD protection device, wherein said third doped region forms an N+ guard ring around an SCR device and said fourth doped region forms said SCR cathode and said fifth doped region forms a source region and said sixth doped region forms a drain region, and said source and drain regions adjacent to said first FET gate element to form an NFET device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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Specification