Flexible and elastic dielectric integrated circuit

• US 7,911,012 B2
• Filed: 01/18/2008
• Issued: 03/22/2011
• Est. Priority Date: 04/08/1992
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Leedy, Glenn
• Primary Examiner(s): CLARK, JASMINE JHIHAN B
• Application Number:
  US12/009,581
• Publication Number:
  US 20080302559A1
• Time in Patent Office: 1,159 Days
• Field of Search: 257/419
• US Class Current: 257/419
• CPC Class Codes: G02F 1/13452 Conductors connecting driver circuitry and terminals of panels
• CPC Class Codes: G02F 1/136281 having a transmissive semiconductor substrate
• CPC Class Codes: G03F 7/70658 Electrical testing
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76289 Lateral isolation by air gap
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 23/538 the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates H05K takes precedence; manufacture or treatment H01L21/4846 ; mountings per se H01L23/12; materials H01L23/49866
• CPC Class Codes: H01L 23/5381 Crossover interconnections, e.g. bridge stepovers
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 23/5387 : Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0207 : Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: Y10S 148/135 : Removal of substrate
• CPC Class Codes: Y10S 438/928 : Front and rear surface processing
• CPC Class Codes: Y10S 438/938 : Lattice strain control or utilization
• CPC Class Codes: Y10S 438/942 : Masking
• CPC Class Codes: Y10S 438/967 : Semiconductor on specified insulator
• CPC Class Codes: Y10S 438/977 : Thinning or removal of substrate
• CPC Class Codes: Y10T 29/49128 : Assembling formed circuit to base
• CPC Class Codes: Y10T 29/49162 : by using wire as conductive path
• CPC Class Codes: Y10T 29/49165 : by forming conductive walled aperture in base
• CPC Class Codes: Y10T 29/49171 : with encapsulating
• CPC Class Codes: Y10T 29/4921 : with bonding

Abstract

General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Claims

1. A circuit interconnect comprising:

a substrate;

at least one of a stress-controlled dielectric layer, a low stress dielectric layer, a flexible dielectric layer and an elastic dielectric layer overlying the substrate; and

a plurality of interconnect conductors formed within the at least one of the stress-controlled dielectric layer, the low stress dielectric layer, the flexible dielectric layer and the elastic dielectric layer, wherein the stress of the at least one of the stress-controlled dielectric layer, the low stress dielectric layer, the flexible dielectric layer and the elastic dielectric layer is at least one of about 8×

10⁸ dynes/cm² or less and 2 to 100 times less than the fracture strength of the at least one of the stress-controlled dielectric layer, the low stress dielectric layer, the flexible dielectric layer and the elastic dielectric layer.

2. The apparatus of claim 1, wherein the substrate is at least one of a semiconductor substrate, a silicon substrate, and a dielectric substrate.

3. The apparatus of claim 1, wherein the stress is tensile.

4. The apparatus of claim 1, wherein the interconnect conductors are at least one of electrical and optical interconnect conductors.

5. The apparatus of claim 1, wherein the substrate is removed.

6. The apparatus of claim 1, wherein a substantial portion of the substrate is removed.

7. The apparatus of claim 1 further comprising, removing the substrate, wherein the remaining circuit interconnect is at least one of a substantially flexible interconnect circuit, an elastic interconnect circuit and a free standing interconnect circuit.

8. The apparatus of claim 1, wherein a substantial portion of the substrate is able to be removed throughout a full extent thereof while retaining the structural integrity of the circuit interconnect.

9. The apparatus of claim 1, wherein the circuit interconnect is able to be thinned to about 50 microns or less while retaining its structural integrity.

10. The apparatus of claim 1, wherein the circuit interconnect has a thickness of about 50 microns or less.

11. The apparatus of claim 1, further comprising:

one or more integrated circuits overlying the circuit interconnect; and

interconnect connecting at least one of the one or more integrated circuits and at least one of the plurality of interconnect conductors of the circuit interconnect.

12. The apparatus of claim 1, further comprising at least one flexible integrated circuit overlying the circuit interconnect.

13. The apparatus of claim 1, wherein the circuit interconnect is at least one of elastic and substantially flexible.

14. The apparatus of claim 1, wherein the at least one of the stress-controlled dielectric layer, the low stress dielectric layer, the flexible dielectric layer and the elastic dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.

15. The apparatus of claim 1, wherein the at least one of the stress-controlled dielectric layer, the low stress dielectric layer, the flexible dielectric layer and the elastic dielectric layer is at least one of an inorganic dielectric material, an organic dielectric material, elastic and substantially flexible.

16. The apparatus of claim 15, wherein the inorganic dielectric material is at least one of an oxide of silicon, a nitride of silicon, silicon dioxide and silicon nitride.

17. The apparatus of claim 1, wherein the at least one of the stress-controlled dielectric layer, the low stress dielectric layer, flexible dielectric layer and the elastic dielectric layer is formed by at least one of Chemical Vapor Deposition, Plasma Enhanced Chemical Vapor Deposition, multiple RF energy sources and at a temperature of about 400°

C.

18. An electric interconnect structure for interconnecting the active regions of transistors formed in a semiconductor substrate and passive regions so as to form an integrated circuit, said interconnect structure comprising:

at least one of a stress-controlled dielectric layer, a low stress dielectric layer, a flexible dielectric layer and an elastic dielectric layer overlying the substrate; and

at least one layer of electrical conductors formed on or directly adjacent to at least one of the stress-controlled dielectric layer, the low stress dielectric layer, the flexible dielectric layer and the elastic dielectric layer, wherein the stress of the at least one of the stress-controlled dielectric layer, the low stress dielectric layer, the flexible dielectric layer and the elastic dielectric layer is at least one of about 8×

10⁸ dynes/cm² or less and 2 to 100 times less than the fracture strength of the at least one of the stress-controlled dielectric layer, the low stress dielectric layer, the flexible dielectric layer and the elastic dielectric layer.

19. The apparatus of claim 18, wherein the substrate is at least one of a semiconductor substrate, a silicon substrate, and a dielectric substrate.

20. The apparatus of claim 18, wherein the stress is tensile.

21. The apparatus of claim 18, wherein the electrical conductors are at least one of electrical and optical interconnect conductors.

22. The apparatus of claim 18, wherein the substrate is removed.

23. The apparatus of claim 18, wherein a substantial portion of the substrate is removed.

24. The apparatus of claim 18, further comprising removing the substrate, wherein the remaining interconnect structure is at least one of a substantially flexible interconnect circuit, an elastic interconnect circuit and a free standing interconnect circuit.

25. The apparatus of claim 18, wherein a substantial portion of the substrate is able to be removed throughout a full extent thereof while retaining the structural integrity of the interconnect structure.

26. The apparatus of claim 18, wherein the interconnect structure is able to be thinned to about 50 microns or less while retaining its structural integrity.

27. The apparatus of claim 18, wherein the interconnect structure has a thickness of about 50 microns or less.

28. The apparatus of claim 18, wherein the interconnect structure has a thickness of about 50 microns or less.

29. The apparatus of claim 18, further comprising:

one or more integrated circuits overlying the interconnect structure; and

interconnect connecting at least one of the one or more integrated circuits and at least one of the plurality of interconnect conductors of the interconnect structure.

30. The apparatus of claim 18, further comprising at least one flexible integrated circuit overlying the interconnect structure.

31. The apparatus of claim 18, wherein the interconnect structure is at least one of elastic and substantially flexible.

32. The apparatus of claim 18, wherein the at least one of the stress-controlled dielectric layer, the low stress dielectric layer, the flexible dielectric layer and the elastic dielectric layer is capable of forming at least one of a flexible membrane, an elastic membrane and a free standing membrane.

33. The apparatus of claim 18, wherein the at least one of the stress-controlled dielectric layer, the low stress dielectric layer, the flexible dielectric layer and the elastic dielectric layer is at least one of an inorganic dielectric material, an organic dielectric material, elastic and substantially flexible.

34. The apparatus of claim 33, wherein the inorganic dielectric material is at least one of an oxide of silicon, a nitride of silicon, silicon dioxide and silicon nitride.

35. The apparatus of claim 18, wherein the at least one of the stress-controlled dielectric layer, the low stress dielectric layer, flexible dielectric layer and the elastic dielectric layer is formed by at least one of Chemical Vapor Deposition, Plasma Enhanced Chemical Vapor Deposition, multiple RF energy sources and at a temperature of about 400°

C.