Semiconductor chip having island dispersion structure and method for manufacturing the same

• US 7,911,058 B2
• Filed: 11/15/2006
• Issued: 03/22/2011
• Est. Priority Date: 11/30/2005
• Status: Expired due to Fees

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Aoki, Shigeru, Oyu, Kiyonori
• Primary Examiner(s): Richards; N Drew
• Assistant Examiner(s): Trinh; Hoa B
• Application Number:
  US11/599,268
• Publication Number:
  US 20070120255A1
• Time in Patent Office: 1,588 Days
• Field of Search: 257/763, 257/774, 257/758, 257/E23.01, 257/750, 257/734, 257/737, 257/738, 257779-781, 257/786
• US Class Current: 257/750
• CPC Class Codes: H01L 21/306 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/31
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 23/26 including materials for absorbing or reacting with moisture or other undesired substances , e.g. getters
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention has an object to provide a semiconductor chip of high reliability with less risk of breakage. Specifically, the present invention provides a semiconductor chip having a semiconductor silicon substrate including a semiconductor device layer and a porous silicon domain layer, the semiconductor device layer being provided in a main surface region on one surface of the semiconductor silicon substrate, the porous silicon domain layer being provided in a main surface region on a back surface which is the other surface of the semiconductor silicon substrate, and the porous silicon domain layer having porous silicon domains dispersed like islands in the back surface of the semiconductor silicon substrate.

Claims

1. A semiconductor chip including a semiconductor silicon substrate having a semiconductor device layer and a dimple layer,

said semiconductor device layer being provided in a main surface region on one surface of the semiconductor silicon substrate and including at least one transistor,

said dimple layer being provided in a main surface region on a back surface which is another surface of the semiconductor silicon substrate, and

said dimple layer having a plurality of dimples dispersed in the back surface of the semiconductor silicon substrate, and

said semiconductor chip further comprising a porous silicon layer on the back surface.

2. The semiconductor chip of claim 1, wherein each of the dimples has substantially the same area as a circle having a diameter ranging from 0.2 to 800 μ

m.

3. The semiconductor chip of claim 1, wherein a total area of the dimples ranges from 10% to 90% of an area of the back surface.

4. A semiconductor device including the semiconductor chip of claim 1.

5. The semiconductor chip of claim 1, wherein the porous silicon layer being formed over substantially entire area of the back surface.