Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules

• US 7,911,819 B2
• Filed: 07/24/2008
• Issued: 03/22/2011
• Est. Priority Date: 05/08/2003
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M., Lee, Terry R.
• Primary Examiner(s): Nguyen; Viet Q
• Application Number:
  US12/179,423
• Publication Number:
  US 20090073647A1
• Time in Patent Office: 971 Days
• Field of Search: 365/63, 714/764, 714/773, 711/104, 711/170, 711/173, 711/211, 710/107, 710/305
• US Class Current: 365/63
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 2201/09972 Partitioned, e.g. portions of a PCB dedicated to different functions; Boundary lines therefore; Portions of a PCB being processed separately or differently
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time. In an alternate embodiment, the printed circuit board includes a driver sector electrically isolated from the other sectors and having a multi-layer structure, the driver being attached to the driver sector.

Claims

1. A memory module for use in a computer system having a memory interface, comprising:

a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure;

at least one memory device attached to each sector of the printed circuit board, the memory devices being organized into a plurality of memory ranks; and

at least one driver attached to the printed circuit board and coupled to at least one of the memory devices from each of the memory ranks, the driver configured to be coupled to the memory interface, wherein the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory ranks on a particular sector may be accessed at one time.

2. The memory module according to claim 1 wherein each sector has first and second sides, and wherein the at least one memory device attached to each sector comprises at least one memory device attached to each of the first and second sides.

3. The memory module according to claim 1 wherein the plurality of sectors comprises four sectors and wherein the at least one driver comprises four drivers, each driver being attached to one of the sectors.

4. The memory module according to claim 3 wherein the at least one memory device attached to each sector comprises four memory devices attached to each of the four sectors.

5. The memory module according to claim 4 wherein the first, fifth, ninth, and thirteenth memory devices are attached to the first sector, and wherein the second, sixth, tenth, and fourteenth memory devices are attached to the second sector, and wherein the third, seventh, eleventh, and fifteenth memory devices are attached to the third sector, and wherein the fourth, eighth, twelfth, and sixteenth memory devices are attached to the fourth sector, and wherein a first memory rank includes the first, second, third, and fourth memory devices, a second memory rank includes the fifth, sixth, seventh, and eighth memory devices, a third memory rank includes the ninth, tenth, eleventh, and twelfth memory devices, and a fourth memory rank includes the thirteenth, fourteenth, fifteenth, and sixteenth memory devices.

6. The memory module according to claim 1 wherein the printed circuit board comprises a driver sector electrically isolated from the other sectors and having a multi-layer structure, the driver being attached to the driver sector.

7. The memory module according to claim 1 wherein the plurality of sectors comprises four sectors and wherein the at least one driver comprises a single driver.

8. The memory module according to claim 7 wherein the at least one memory device attached to each sector comprises four memory devices attached to each sector.

9. The memory module according to claim 8 wherein the first, fifth, ninth, and thirteenth memory devices are attached to the first sector, the second, sixth, tenth, and fourteenth memory devices are attached to the second sector, the third, seventh, eleventh, and fifteenth memory devices are attached to the third sector, and the fourth, eighth, twelfth, and sixteenth memory devices are attached to the fourth sector, and wherein a first memory rank includes the first, second, third, and fourth memory devices, a second memory rank includes the fifth, sixth, seventh, and eighth memory devices, a third memory rank includes the ninth, tenth, eleventh, and twelfth memory devices, and a fourth memory rank includes the thirteenth, fourteenth, fifteenth, and sixteenth memory devices.

10. The memory module according to claim 1 wherein the printed circuit board includes a connector edge adapted for insertion into a motherboard.

11. The memory module according to claim 1 wherein the driver comprises a hub including a plurality of driver chips.

12. The memory module according to claim 1 wherein the multi-layer structure of the printed circuit board includes first, second, third, and fourth signal layers, first and second ground layers, and first and second power supply layers.

13. The memory module according to claim 1 wherein the multi-layer structure of the printed circuit board includes first, second, third, and fourth signal layers, a ground layer, and a power supply layer.

14. The memory module according to claim 1 wherein the driver is adapted to receive electrical signals from the memory interface.

15. The memory module according to claim 1 wherein the driver is adapted to receive optical signals from the memory interface.

16. The memory module according to claim 1 wherein the driver is adapted to receive RF signals from the memory interface.

17. A computer system, comprising:

a central processing unit;

a system memory; and

a bus bridge coupled to the central processing unit and the system memory and configured to allow communication between the central processing unit and the system memory, wherein the system memory includes at least one memory module comprising;

a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure;

at least one memory device attached to each sector of the printed circuit board, the memory devices being organized into a plurality of memory ranks; and

at least one driver attached to the printed circuit board and coupled to at least one of the memory devices from each of the memory ranks and to the bus bridge, wherein the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory ranks on a particular module may be accessed at one time.

18. The computer system according to claim 17 wherein each sector has first and second sides, and wherein the at least one memory device attached to each sector comprises at least one memory device attached to each of the first and second sides.

19. The computer system according to claim 17 wherein the plurality of sectors comprises four sectors and wherein the at least one driver comprises four drivers, each driver being attached to one of the sectors.

20. The computer system according to claim 19 wherein the at least one memory device attached to each sector comprises four memory devices attached to each of the four sectors.

21. The computer system according to claim 20 wherein the first, fifth, ninth, and thirteenth memory devices are attached to the first sector, and wherein the second, sixth, tenth, and fourteenth memory devices are attached to the second sector, and wherein the third, seventh, eleventh, and fifteenth memory devices are attached to the third sector, and wherein the fourth, eighth, twelfth, and sixteenth memory devices are attached to the fourth sector, and wherein a first memory rank includes the first, second, third, and fourth memory devices, a second memory rank includes the fifth, sixth, seventh, and eighth memory devices, a third memory rank includes the ninth, tenth, eleventh, and twelfth memory devices, and a fourth memory rank includes the thirteenth, fourteenth, fifteenth, and sixteenth memory devices.

22. The computer system according to claim 17 wherein the printed circuit board comprises a driver sector electrically isolated from the other sectors and having a multi-layer structure, the driver being attached to the driver sector.

23. The computer system according to claim 17 wherein the plurality of sectors comprises four sectors and wherein the at least one driver comprises a single driver.

24. The computer system according to claim 23 wherein the at least one memory device attached to each sector comprises four memory devices attached to each sector.

25. The computer system according to claim 24 wherein the first, fifth, ninth, and thirteenth memory devices are attached to the first sector, the second, sixth, tenth, and fourteenth memory devices are attached to the second sector, the third, seventh, eleventh, and fifteenth memory devices are attached to the third sector, and the fourth, eighth, twelfth, and sixteenth memory devices are attached to the fourth sector, and wherein a first memory rank includes the first, second, third, and fourth memory devices, a second memory rank includes the fifth, sixth, seventh, and eighth memory devices, a third memory rank includes the ninth, tenth, eleventh, and twelfth memory devices, and a fourth memory rank includes the thirteenth, fourteenth, fifteenth, and sixteenth memory devices.

26. The computer system according to claim 17 wherein the system memory includes a motherboard and the printed circuit board includes a connector edge inserted into the motherboard.

27. The computer system according to claim 17 wherein the system memory includes a motherboard that includes a second plurality of electrically-isolated sectors corresponding to the electrically-isolated sectors of the printed circuit board.

28. The computer system according to claim 17 wherein the driver comprises a hub including a plurality of driver chips.

29. The computer system according to claim 17 wherein the multi-layer structure of the printed circuit board includes first, second, third, and fourth signal layers, first and second ground layers, and first and second power supply layers.

30. The computer system according to claim 17 wherein the multi-layer structure of the printed circuit board includes first, second, third, and fourth signal layers, a ground layer, and a power supply layer.

31. The computer system according to claim 17, further comprising a display coupled to the bus bridge.

32. The computer system according to claim 17, further comprising a user input device coupled to the bus bridge.

33. The computer system according to claim 17 wherein the at least one driver is adapted to receive electrical signals from the bus bridge.

34. The computer system according to claim 17 wherein the at least one driver is adapted to receive optical signals from the bus bridge.

35. The computer system according to claim 17 wherein the at least one driver is adapted to receive RF signals from the bus bridge.

36. A method of accessing and processing data in a system memory coupled to a data bus of a computer system, comprising:

providing a memory module having a printed circuit board that includes a plurality of electrically-isolated sectors, each sector having at least one memory device attached thereto;

receiving a plurality of command signals and a plurality of address signals via the bus;

processing the plurality of command signals and plurality of address signals; and

simultaneously accessing two or more memory devices of different sectors based on the plurality of command signals and plurality of address signals.

37. The method according to claim 36 wherein receiving a plurality of command signals and a plurality of address signals via the bus comprises receiving a plurality of command signals and a plurality of address signals into a driver chip.

38. The method according to claim 36 wherein receiving a plurality of command signals and a plurality of address signals via the bus comprises receiving a plurality of command signals and a plurality of address signals into a plurality of driver chips.

39. The method according to claim 36 wherein processing the plurality of command signals and plurality of address signals comprises processing the plurality of command signals and plurality of address signals using a plurality of a driver chips.

40. The method according to claim 36 wherein processing the plurality of command signals and plurality of address signals comprises multiplexing the plurality of command signals and plurality of address signals.

41. The method according to claim 36 wherein simultaneously accessing two or more memory devices of different sectors based on the plurality of command signals and plurality of address signals comprises simultaneously accessing one of the memory devices attached to each sector.

42. The method according to claim 36 wherein simultaneously accessing two or more memory devices of different sectors based on the plurality of command signals and plurality of address signals comprises simultaneously writing to two or more memory devices.

43. The method according to claim 36 wherein simultaneously accessing two or more memory devices of different sectors based on the plurality of command signals and plurality of address signals comprises simultaneously reading from two or more memory devices.

44. The method according to claim 36 wherein accessing one or more memory devices of a particular sector comprises individually accessing one or more memory devices of the particular sector, further comprising accessing one or more memory devices of another of the plurality of electrically-isolated sectors.

45. The method according to claim 36 wherein receiving a plurality of command signals and a plurality of address signals via the bus comprises receiving a plurality electrical signals.

46. The method according to claim 36 wherein receiving a plurality of command signals and a plurality of address signals via the bus comprises receiving a plurality optical signals.

47. The method according to claim 36 wherein receiving a plurality of command signals and a plurality of address signals via the bus comprises receiving a plurality RF signals.