Method and system for providing low cost robust operational control of video encoders

• US 7,912,123 B2
• Filed: 03/01/2006
• Issued: 03/22/2011
• Est. Priority Date: 03/01/2006
• Status: Active Grant

• Current Assignee: Streaming Networks PVT Limited
• Original Assignee: Streaming Networks PVT Limited
• Inventors: ul-Haq, Imran, Shafique, Muhammad, Ziauddin, Syed Muhammad, Nadeem, Muhammad
• Primary Examiner(s): Tran; Khai
• Application Number:
  US11/366,320
• Publication Number:
  US 20070206674A1
• Time in Patent Office: 1,847 Days
• Field of Search: 375/240.05, 375/240.01, 375/240.06, 375/240.16, 375/240.27, 382/326, 382/238, 382/239
• US Class Current: 375/240.05
• CPC Class Codes: H04N 19/124 Quantisation
• CPC Class Codes: H04N 19/14 Coding unit complexity, e.g. amount of activity or edge presence estimation H04N19/146 takes precedence
• CPC Class Codes: H04N 19/147 according to rate distortion criteria rate-distortion as a criterion for motion estimation H04N19/567
• CPC Class Codes: H04N 19/152 by measuring the fullness of the transmission buffer
• CPC Class Codes: H04N 19/154 Measured or subjectively estimated visual quality after decoding, e.g. measurement of distortion use of rate-distortion criteria H04N19/147
• CPC Class Codes: H04N 19/172 the region being a picture, frame or field
• CPC Class Codes: H04N 19/174 the region being a slice, e.g. a line of blocks or a group of blocks
• CPC Class Codes: H04N 19/176 the region being a block, e.g. a macroblock
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

The present invention discloses a simple low cost framework for robust operational control of video encoders. The framework comprises a two-layer architecture that effectively decouples the processes of video bit rate control and video quality/distortion control. The upper layer includes a video bit rate controller that operates on a single picture/picture-slice, or a set of pictures/picture-slices, and is based on feedback control techniques used in automatic control systems. The lower layer includes a video quality/distortion controller that operates at the level of blocks of pixels, and reduces distortion artifacts. The decoupled nature of the encoder control architecture of the present invention provides the flexibility of combining various feedback control algorithms and various distortion reduction schemes.

Claims

1. A system comprising:

a bit rate controller configured to generate at least one picture/slice quantization parameter based on a feedback control technique, wherein the feedback control technique utilizes at least one of a proportional-integral-derivative (PID) controller, an adaptive controller and a non-adaptive controller;

a quality/distortion controller configured to at least one quality/distortion control signal that controls the selection of at least one of a pixel-block quantization parameter, pixel-block encoding mode and pixel-block partition; and

a video encoder configured to (i) receive the at least one picture/slice quantization parameter and the at least one quality/distortion control signal and (ii) generate encoded video data.

2. The system of claim 1 wherein the system is implemented in software or hardware or a combination of both.

3. The system of claim 1 wherein the PID controller has fixed gains and operates in accordance with the feedback control technique, and wherein values of the fixed gains are predetermined.

4. The system of claim 1 wherein the PID controller has variable gains and operates in accordance with the feedback control technique, and wherein values of the variable gains are updated during operation of the PID controller.

5. The system of claim 1 further comprising a video encoder buffer, wherein state information with respect to the video encoder buffer is used to control the bit rate controller in order to prevent one or more of buffer overflow and underflow.

6. The system of claim 1 wherein information with respect to selection of picture/slice types is used to control the bit rate controller.

7. The system of claim 1 wherein the bit rate controller is further configured to operate within a single pass video encoding system or a multiple pass video encoding system.

8. The system of claim 1 wherein the video encoder is further configured to encode on a real-time or non-real-time basis and generate data streams at a constant bit rate or at a variable bit rate.

9. The system of claim 1 wherein the quality/distortion controller is further configured to receive data that influences a human visual system (HVS), the data including a measure of at least one of a brightness, variance, distortion, and motion activity in at least one pixel block.

10. The system of claim 1 wherein the measure is obtained from at least one a video image, a scaled-down version of the video image, and a sub-sampled version of the video image.

11. The system of claim 1 further comprising a video encoder buffer, wherein state information with respect to the video encoder buffer is used to control the quality/distortion controller in order to prevent one or more of buffer overflow and underflow.

12. The system of claim 1 wherein the quality/distortion controller is further configured to handle one or more processes including a pixel block mode selection process, pixel block partition selection process, and a pixel block quantizer selection process;

and

wherein the one or more processes involve a plurality of comparisons between data that influences a human visual system (HVS) and a plurality of constants and functions.

13. The system of claim 12 wherein the plurality of constants and functions used in the comparisons are predetermined.

14. The system of claim 12 wherein the one or more processes are handled on a binary decision basis.

15. The system of claim 1 wherein the video encoder is compliant with at least one video coding standard including H.264/AVC, VC-1, MPEG-4, MPEG-2, MPEG-1 and H.263.

16. The system of claim 1 wherein the quality/distortion controller is based upon a rate-distortion (RD) optimization method.

17. The system of claim 1 wherein the bit rate controller and the quality/distortion controller are decoupled from one another.

18. The system of claim 1 wherein the bit rate controller operates at a picture/slice level.

19. The system of claim 1 wherein the quality/distortion controller operates at a pixel block level.