Securing non-volatile data in an embedded memory device

• US 7,913,049 B2
• Filed: 10/18/2010
• Issued: 03/22/2011
• Est. Priority Date: 01/10/2008
• Status: Expired due to Fees

• Current Assignee: Unity Semiconductor Corporation (Rambus Inc.)
• Original Assignee: Unity Semiconductor Corporation (Rambus Inc.)
• Inventors: Norman, Robert
• Primary Examiner(s): CHOE, YONG J
• Application Number:
  US12/925,373
• Publication Number:
  US 20110040945A1
• Time in Patent Office: 155 Days
• Field of Search: 711/163, 711/E12.093, 713/190, 365/129
• US Class Current: 711/163
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells

Abstract

The various embodiments of the invention relate generally to semiconductors and memory technology. More specifically, the various embodiment and examples of the invention relate to memory devices, systems, and methods that protect data stored in one or more memory devices from unauthorized access. The memory device may include third dimension memory that is positioned on top of a logic layer that includes active circuitry in communication with the third dimension memory. The third dimension memory may include multiple layers of memory that are vertically stacked upon each other. Each layer of memory may include a plurality of two-terminal memory elements and the two-terminal memory elements can be arranged in a two-terminal cross-point array configuration. At least a portion of one or more of the multiple layers of memory may include an obfuscation layer configured to conceal data stored in one or more of the multiple layers of memory.

Claims

1. A secure non-volatile memory device, comprising:

a silicon semiconductor substrate including active circuitry fabricated on a logic plane of the silicon semiconductor substrate;

a memory layer in contact with and fabricated directly above the silicon semiconductor substrate;

at least one two-terminal cross-point memory array embedded in the memory layer, each array including a plurality of first conductive array lines that are oriented orthogonally to a plurality of second conductive array lines, the plurality of first and second conductive array lines are electrically coupled with at least a portion of the active circuitry;

a plurality of two-terminal memory elements operative to retain stored data, each memory element positioned between a cross-point of one of the plurality of first conductive array lines with one of the plurality of second conductive array lines and including first and second terminals electrically coupled with the first and second conductive array lines respectively, each memory element including an electrolytic tunnel barrier and a conductive metal oxide including mobile oxygen ions, the conductive metal oxide and the electrolytic tunnel barrier are in contact with each other and are electrically in series with the first and second terminals;

a memory storage controller in electrical communication with the at least one two-terminal cross-point memory array and configured to control data operations access to the at least one two-terminal cross-point memory array; and

a device access determinator in electrical communication with the memory storage controller and a validation signal, the device access determinator configured to determine a geographical location of the memory layer, to detect a validation signal, and to grant access to the memory storage controller as a function of the validation signal.

2. The memory device of claim 1, wherein the memory storage controller and the device access determinator are included in the active circuitry.

3. The memory device of claim 1, wherein the silicon semiconductor substrate, the memory storage controller, and the device access determinator are positioned in a plurality of integrated circuit chips.

4. The memory device of claim 3, wherein either the memory storage controller or the device access determinator, or both, are positioned in at least one integrated circuit chip that excludes the silicon semiconductor substrate.

5. The memory device of claim 1, wherein the device access determinator is further configured to detect one or more signals and to revoke access to the memory storage controller as a function of the one or more signals.

6. The memory device of claim 1, wherein the device access determinator includes a device communication interface configured to receive a signal, and a determination logic,

wherein the device access determinator is configured to use the signal to determine a geographical location of the memory layer,

wherein the determination logic is configured to determine whether to grant access to the memory storage controller based on the geographical location of the memory layer.

7. The memory device of claim 6, wherein the determination logic is configured to access proximity data.

8. The memory device of claim 6, wherein the device access determinator is further configured to require a password to grant access to the memory storage controller.

9. The memory device of claim 1 and further comprising:

a plurality of the memory layers in contact with one another and vertically stacked upon one another and the plurality of the memory layers include at least an upper layer and a lower layer.

10. The memory device of claim 9, wherein the upper layer is configured to store either encrypted data or no data, and wherein the memory storage controller and the device access determinator are included in the active circuitry of the logic layer.

11. A system for securing data, comprising:

a signal communicating device operative to electrically communicate an activation signal;

a silicon semiconductor substrate including active circuitry fabricated on a logic plane of the silicon semiconductor substrate;

a non-volatile memory device in contact with and fabricated directly above the silicon semiconductor substrate;

at least one two-terminal cross-point memory array embedded in the non-volatile memory device, each array including a plurality of first conductive array lines that are oriented orthogonally to a plurality of second conductive array lines, the plurality of first and second conductive array lines are electrically coupled with at least a portion of the active circuitry; and

a plurality of two-terminal memory elements operative to retain stored data, each memory element positioned between a cross-point of one of the plurality of first conductive array lines with one of the plurality of second conductive array lines and including first and second terminals electrically coupled with the first and second conductive array lines respectively, each memory element including an electrolytic tunnel barrier and a conductive metal oxide including mobile oxygen ions, the conductive metal oxide and the electrolytic tunnel barrier are in contact with each other and are electrically in series with the first and second terminals,

wherein the active circuitry includes

a signal receiver configured to receive the activation signal, and

determination logic configured to determine a geographical location of the non-volatile memory device, and

wherein data operations access to the non-volatile memory device is granted or denied as a function of the activation signal and the geographical location of the memory device.

12. The system of claim 11, wherein the non-volatile memory device comprises a plurality of memory layers that are in contact with one another and vertically stacked upon one another, and one or more of the two-terminal cross-point memory arrays is embedded in each memory layer.

13. The system of claim 11, wherein the determination logic is configured to

access data representing authorized geographical regions stored in the non-volatile memory device, and

determine whether the activation signal includes positional data.

14. A method for securing a memory device, comprising:

providing a silicon semiconductor substrate including active circuitry fabricated on a logic plane of the silicon semiconductor substrate and a plurality of vertically stacked memory layers that are in contact with one another and are fabricated directly above the silicon semiconductor substrate, each memory layer including at least one two-terminal cross-point memory array embedded in the memory layer, each array including a plurality of first conductive array lines that are oriented orthogonally to a plurality of second conductive array lines, the plurality of first and second conductive array lines are electrically coupled with at least a portion of the active circuitry,

each array including a plurality of two-terminal memory elements operative to retain stored data, each memory element positioned between a cross-point of one of the plurality of first conductive array lines with one of the plurality of second conductive array lines and including first and second terminals electrically coupled with the first and second conductive array lines respectively, each memory element including an electrolytic tunnel barrier and a conductive metal oxide including mobile oxygen ions, the a conductive metal oxide and the electrolytic tunnel barrier are in contact with each other and are electrically in series with the first and second terminals;

determining a geographical location for the silicon semiconductor substrate as a function of signal data; and

granting data operations access to the plurality of vertically stacked memory layers based upon the geographical location being associated with at least a subset of proximity data.

15. The method of claim 14, wherein the subset of proximity data comprises positional data and the signal data comprises authorization data.

16. The method of claim 14, wherein determining the geographical location as the function of the signal data comprises associating the signal data from an activation signal with the subset of proximity data.

17. The method of claim 14 and further comprising:

generating, in response to the granting data operations access to the plurality of vertically stacked memory layers, an acknowledgment signal configured to notify a source of the signal data.

18. The method of claim 17 further and comprising:

generating an alert signal if the acknowledgment signal is not generated.

19. The method of claim 14 and further comprising:

receiving a shutdown signal configured to revoke the data operations access; and

revoking the data operations access to the plurality of vertically stacked memory layers.

20. The method of claim 19 and further comprising:

a memory storage controller included in the active circuitry and configured to receive at least one signal, the memory storage controller operative to initiate the revoking or the granting of the data operations access as a function of the at least one signal.