Electronic circuit with a memory matrix that stores pages including extra data

• US 7,913,110 B2
• Filed: 03/05/2007
• Issued: 03/22/2011
• Est. Priority Date: 03/07/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Van Acht, Victor M. G., Lambert, Nicolaas
• Primary Examiner(s): Duncan, Marc
• Application Number:
  US12/281,983
• Publication Number:
  US 20090070637A1
• Time in Patent Office: 1,478 Days
• Field of Search: 714/6, 714/764, 714/766, 714/768
• US Class Current: 714/6.1
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence

Abstract

An apparatus comprises a memory with a matrix (10) with rows and columns of memory cells. A read access circuit (14, 16, 18) executes a read command to read a retrieval unit comprising data from a row of the memory cells from the matrix (10) and to output data from the retrieval unit. A processing circuit (12) coupled to the read access circuit (14, 16, 18) is configured to execute an extra read operation involving issuing the read command, receiving the extra data (24), performing error detection on only the extra data (24), using an error detecting code in which the extra data is coded, conditionally performing error correction on the data from the extra data (24) using data from the retrieval unit including the payload data (22), according to an error correcting code in which the retrieval unit is coded, if the error detection indicates an error in the extra data (24). The processing circuit (12) performs further processing using the data from the extra data (22) or the corrected extra data, dependent on whether the error detection indicates an error in the extra data (22).

Claims

1. An apparatus comprising:

a memory comprising a matrix with rows and columns of memory cells;

a read access circuit configured to execute a read command to read a retrieval unit comprising data from a row of the memory cells from the matrix and to output data from the retrieval unit, the data in the retrieval unit comprising payload data and addressable extra data outside an address space for the payload data;

a processing circuit coupled to the read access circuit and configured to execute an extra read process comprising issuing the read command, receiving the extra data, to perform error detection on only the extra data, making use of an error detecting code in which the extra data is coded, conditionally performing error correction on the data from the extra data using data from the retrieval unit including the payload data, according to an error correcting code in which the retrieval unit is coded, if the error detection indicates an error in the extra data, the processing circuit being configured to perform further processing using the data from the extra data or the corrected extra data, dependent on whether the error detection indicates an error in the extra data;

wherein the read access circuit is configured to read the retrieval unit and to serially output data from the retrieval unit in response to the read command, the processing circuit being configured to obtain the extra data from a part of the retrieval unit that is output in response to the read command at least partly before the payload data, and causing the output to cease if the error detection indicates absence of an error in the extra data.

2. An apparatus according to claim 1, wherein the read access circuit is configured to support execution of a normal read operation, when the payload data is needed for payload data processing, by reading the payload data and the extra data and performing error correction on the payload data using data from the payload data and the extra data according to the error correcting code.

3. An apparatus according to claim 1, wherein a first error correcting capacity of the error correcting code that the processing circuit is configured to use is higher than a second error correcting capacity, if any, of the error detecting code that the processing circuit is configured to use.

4. An apparatus according to claim 1, wherein the processing circuit is configured to receive the payload data for writing, the payload data being associated with a logical address for the payload data, to select a physical address corresponding to the retrieval unit for the payload data, and to include information about the logical address in the extra data.

5. A method of operating a memory comprising a matrix with rows and columns of memory cells, the method comprising

writing data to a retrieval unit that comprises at least one of the rows, the data comprising payload data and extra data outside an address space for the payload data, the payload data and the extra data together being part of a codeword of an error correcting code, the extra data being selected from codewords of an error detecting code;

reading the data from the retrieval unit,

performing error detection on only the extra data using the error detecting code;

conditionally performing error correction on the data from the extra data using the payload data and the extra data from the retrieval unit according to the error correcting code, if the error detection indicates an error in the extra data;

performing further processing using the data from the extra data or the corrected extra data, dependent on whether the error detection indicates an error in the extra data;

the method comprising

issuing a read command to the memory, which causes the memory to read the retrieval unit and to serially output data from the retrieval unit, the extra data being output at least partly before the payload data in response to the read command, if the output is not made to cease;

causing the output to cease if the error detection indicates absence of an error in the extra data.

6. A method according to claim 5, the method comprising reading the payload data and the extra data when the payload data is needed for payload data processing and performing error correction on the payload data using data from the payload data and the extra data from the retrieval unit according to the error correcting code.

7. A method according to claim 5, wherein a first error correcting capacity of the error correcting code that is used is higher than a second error correcting capacity, if any, of the error detecting code that is used.

8. A method according to claim 5, comprising receiving the payload data in association with a logical address for the payload data, selecting a physical address in the matrix for the retrieval unit for the payload data and including information about the logical address in the extra data.