System and method for on-board diagnostics of memory modules

• US 7,913,122 B2
• Filed: 12/30/2008
• Issued: 03/22/2011
• Est. Priority Date: 08/19/2003
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Round Rock Research LLC
• Inventors: Jeddeloh, Joseph M.
• Primary Examiner(s): Bonzo; Bryce P
• Application Number:
  US12/346,216
• Publication Number:
  US 20090106591A1
• Time in Patent Office: 812 Days
• Field of Search: 714/42
• US Class Current: 714/42
• CPC Class Codes: G11C 2029/5602 Interface to device under test
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 29/56004 Pattern generation
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

A memory hub includes an on-board diagnostic engine through which diagnostic testing and evaluation of the memory system can be performed. The memory hub includes a link interface for receiving memory requests for access to memory devices of the memory system and a memory device interface coupled to the memory devices for coupling memory requests to the memory devices. A memory hub diagnostic engine is coupled through a switch to the link interface and the memory device interface to perform diagnostic testing of the memory system. The diagnostic engine includes a maintenance port that provides access to results of the diagnostic testing and through which diagnostic testing commands can be received.

Claims

1. A system comprising:

a plurality of memory systems, each of the memory systems including a respective plurality of memory devices and logic coupled to the memory devices, the logic comprising;

a memory device interface configured to provide signals to the memory devices and receive signals from the memory devices;

a diagnostic test engine coupled to the memory device interface and configured to receive diagnostic testing commands and monitor memory system operation while at least one of the memory devices is operating; and

a direct memory access (DMA) engine coupled to the diagnostic test engine, the DMA engine operable to retrieve and load data patterns for testing into the logic.

2. The system of claim 1 wherein the DMA engine is configured to store signal trace history for at least one of the signals sent to the memory devices for retrieval through the host computer system interface.

3. A system comprising:

a plurality of memory systems coupled to a link on which signals are transmitted, each of the memory systems including;

a plurality of memory devices and logic coupled to the memory devices, the logic comprising;

a plurality of link interfaces coupled to the link, the link interfaces configured to transmit and receive control, address and data signals on the link;

a diagnostic test engine coupled to the link interface and configured to receive diagnostic testing commands and provide diagnostic testing results, the diagnostic test engine configured to monitor memory system operation and provide results from monitoring the memory system operation to a host computer system as diagnostic testing results; and

a direct memory access (DMA) engine coupled to the diagnostic test engine, the DMA engine operable to retrieve and load data patterns for testing into the logic.

4. The system of claim 3 wherein the DMA Engine is further configured to store signal trace history for monitored memory system operation for retrieval through the host computer system interface.