On-chip comparison and response collection tools and techniques

• US 7,913,137 B2
• Filed: 02/20/2007
• Issued: 03/22/2011
• Est. Priority Date: 02/17/2006
• Status: Active Grant

• Current Assignee: Novatek Microelectronics Corporation (Novatek Microelectronics Corp Limited)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Mukherjee, Nilanjan, Tyszer, Jerzy, Rajski, Janusz
• Primary Examiner(s): Beausoliel; Robert
• Assistant Examiner(s): Merant; Guerrier
• Application Number:
  US11/709,079
• Publication Number:
  US 20070234163A1
• Time in Patent Office: 1,491 Days
• Field of Search: None
• US Class Current: 714/729
• CPC Class Codes: G01R 31/2851 Testing of integrated circuits [IC] G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318547 Data generators or compressors
• CPC Class Codes: G01R 31/318563 Multiple simultaneous testing of subparts
• CPC Class Codes: G01R 31/318566 Comparators; Diagnosing the device under test

Abstract

Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.

Claims

1. An apparatus for testing a plurality of electronic circuits, the apparatus comprising:

a plurality of scan chain groups, each scan chain group comprising one or more scan chains and one or more corresponding scan chain group outputs;

a plurality of comparator circuits, each comparator circuit comprising a comparator input and a comparator output;

an encoder circuit comprising a plurality of encoder inputs and an encoder output, wherein the encoder inputs are coupled to respective comparator outputs; and

a plurality of compactors, each compactor comprising an XOR or XNOR tree configured to compact test response values output from the scan chain group outputs of a respective one of the scan chain groups, each compactor further comprising two or more compactor inputs coupled to the scan chain group outputs of the respective one of the scan chain groups and further comprising a compactor output coupled to the comparator input of a respective comparator, the encoder circuit being configured to detect more than two error values output from the compactor outputs.

2. The apparatus of claim 1, wherein the encoder circuit is configured to detect the more than two error values output from the compactor outputs during a single shift cycle.

3. The apparatus of claim 1, wherein the encoder circuit is further configured to detect two or fewer error values output from the compactor outputs.

4. The apparatus of claim 1, further comprising a plurality of masking circuits, each masking circuit having a masking circuit input coupled to the comparator output of a respective compactor and a masking output coupled to respective encoder inputs.

5. The apparatus of claim 1, further comprising a memory coupled to the encoder output.