Structure for a duty cycle correction circuit

• US 7,913,199 B2
• Filed: 05/29/2008
• Issued: 03/22/2011
• Est. Priority Date: 07/14/2006
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Qi, Jieming, Hailu, Eskinder, Boerstler, David W.
• Primary Examiner(s): Levin; Naum B
• Application Number:
  US12/128,754
• Publication Number:
  US 20080229270A1
• Time in Patent Office: 1,027 Days
• Field of Search: 716/100, 716/105, 327/175
• US Class Current: 716/100
• CPC Class Codes: H03K 2005/00058 controlled by a digital setting
• CPC Class Codes: H03K 2005/00221 where the conduction path of the different output FET's is connected in parallel with different gate control, e.g. having different sizes or thresholds, or coupled through different resistors
• CPC Class Codes: H03K 5/1565 the output pulses having a constant duty cycle

Abstract

A design structure for a Duty Cycle Correction (DCC) circuit is provide in which pairs of field effect transistors (FETs) in known DCC circuit topologies are replaced with linear resistors coupled to switches of the DCC circuit such that when the switch is open, the input signal is routed through the linear resistors. The linear resistors are more tolerant of process, voltage and temperature (PVT) fluctuations than FETs and thus, the resulting DCC circuit provides a relatively smaller change in DCC correction range with PVT fluctuations than the known DCC circuit topology that employs FETs. The linear resistors may be provided in parallel with the switches and in series with a pair of FETs having relatively large resistance values. The linear resistors provide resistance that pulls-up or pulls-down the pulse width of the input signal so as to provide correction to the duty cycle of the input signal.

Claims

1. A design structure embodied in a machine readable storage device, wherein the design structure is loaded from the storage device into a computer for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

first design structure elements representing a first pair of field effect transistors (FETs) having a first P-type FET and a first N-type FET;

second design structure elements representing at least two linear resistors coupled to the first pair of FETs, wherein a first linear resistor is coupled to the first P-type FET and a second linear resistor is coupled to the first N-type FET;

a third design structure element representing a first switch coupled to the first linear resistor; and

a fourth design structure element representing a second switch coupled to the second linear resistor, wherein the first, second, third, and fourth design structure elements are configured such that an input signal is provided to the first pair of FETs and a corrected input signal is output by the at least two linear resistors, and wherein the first and second switches are selectively controlled so as to cause at least one of the first or second linear resistors to increase or decrease a duty cycle of the input signal.

2. The design structure of claim 1, wherein the design structure is configured such that the first linear resistor is coupled in series to the first P-type FET, the second linear resistor is coupled in series to the first N-type FET, the first switch is coupled to the first linear resistor in parallel, and the second switch is coupled to the second linear resistor in parallel.

3. The design structure of claim 1, wherein the design structure is configured such that a resistance value associated with the first linear resistor is less than approximately ten percent of a resistance value associated with the first P-type FET, and a resistance value associated with the second linear resistor is less than approximately ten percent of a resistance value associated with the first N-type FET.

4. The design structure of claim 1, further comprising:

a fifth design structure element representing a duty cycle detection unit coupled to an input signal line of the duty cycle correction apparatus; and

a sixth design structure element representing a duty cycle control unit coupled to the duty cycle detection unit and the first and second switches, wherein the design structure is configured such that duty cycle detection unit provides a measure of a duty cycle of the input signal to the duty cycle control unit, and the duty cycle control unit controls opening and closing of the first and second switches, so as to provide an appropriate amount of duty cycle correction, based on the measure of the duty cycle of the input signal provided by the duty cycle detection unit and a desired duty cycle for the input signal.

5. The design structure of claim 1, wherein the design structure is configured such that the first linear resistor operates on a signal output by the first P-type FET to thereby pull-up a pulse width of the signal output by the first P-type FET and thereby decrease a duty cycle of the signal output by the P-type FET.

6. The design structure of claim 1, wherein the design structure is configured such that the second linear resistor operates on a signal output by the first N-type FET to thereby pull-down a pulse width of the signal output by the first P-type FET and thereby increase a duty cycle of the signal output by the N-type FET.

7. The design structure of claim 1, wherein the design structure is configured such that if no duty cycle correction is required, both the first switch and the second switch are closed.

8. The design structure of claim 1, wherein the design structure is configured such that if a duty cycle of the input signal is to be decreased, the first switch is opened and the second switch is closed, such that the input signal passes through the first linear resistor.

9. The design structure of claim 1, wherein the design structure is configured such that if a duty cycle of the input signal is to be increased, the first switch is closed and the second switch is opened, such that the input signal passes through the second linear resistor.

10. The design structure of claim 1, further comprising:

fifth design structure elements representing a second pair of FETs coupled to the first and second linear resistors, wherein the design structure is configured such that the second pair of FETs comprise a second P-type FET and a second N-type FET, and the second pair of FETs operate as buffers between successive duty cycle correction stages.

11. The design structure of claim 1, further comprising:

one or more fifth design structure elements representing one or more additional first linear resistors coupled in series with the first linear resistor;

one or more sixth design structure elements representing one or more additional second linear resistors coupled in series with the second linear resistor; and

one or more seventh design structure elements representing one or more additional switches coupled to the one or more additional first and second linear resistors.

12. The design structure of claim 11, further comprising:

an eighth design structure element representing a duty cycle detection unit coupled to an input signal line of the duty cycle correction apparatus; and

a ninth design structure element representing a duty cycle control unit coupled to the duty cycle detection unit, the first and second switches, and the one or more additional switches, wherein the design structure is configured such that the duty cycle detection unit provides a measure of a duty cycle of the input signal to the duty cycle control unit, and the duty cycle control unit controls opening and closing of the first, second, and one or more additional switches, so as to provide an appropriate amount of duty cycle correction, based on the measure of the duty cycle of the input signal provided by the duty cycle detection unit and a desired duty cycle for the input signal.

13. The design structure of claim 1, wherein the design structure comprises a netlist.

14. The design structure of claim 1, wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.