Background thread processing in a multithread digital signal processor

• US 7,913,255 B2
• Filed: 10/20/2005
• Issued: 03/22/2011
• Est. Priority Date: 10/20/2005
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Codrescu, Lucian
• Primary Examiner(s): Puente; Emerson C
• Assistant Examiner(s): Truong; Camquy
• Application Number:
  US11/256,350
• Publication Number:
  US 20070094660A1
• Time in Patent Office: 1,979 Days
• Field of Search: 718/108, 710/262
• US Class Current: 718/101
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

Techniques for the design and use of a digital signal processor, including processing transmissions in a communications (e.g., CDMA) system. The disclosed method and system provide background thread processing in a multithread digital signal processor for backgrounding and other background operations. The method and system form a background thread interrupt as one of a plurality of interrupt types, the background thread interrupt initiates a low-priority background process using one of a plurality of processing threads of a multithread digital signal processor. The process includes storing the background thread interrupt in an interrupt register and a background processing mask for associating with a processing thread of the multithread digital signal processor, which associates with at least a subset of said plurality of processing threads. Upon sensing a cache miss in one of the processing threads during multithread processing, the interrupt register issues the background thread interrupt and the digital signal processor initiates background processing using one of the processing threads having an associated background processing mask.

Claims

1. A method of performing background processing in a multithreaded digital signal processor comprising a plurality of processing threads, said method comprising:

forming a background thread interrupt as one of a plurality of interrupt types, said background thread interrupt to initiate a background process using one of a plurality of processing threads of said multithreaded digital signal processor;

storing said background thread interrupt in an interrupt register;

forming a background processing mask; and

associating said background processing mask with at least a subset of said plurality of processing threads;

sensing a predetermined event in an active thread of said plurality of processing threads during processing of said multithreaded digital signal processor;

issuing said background thread interrupt from said interrupt register in response to said predetermined event;

initiating background processing using an idle thread of said subset of said plurality of processing threads having an associated background process mask, wherein said multithreaded digital signal processor is operable to support concurrent execution of two or more of said plurality of processing threads;

storing said background thread interrupt as a background prefetch interrupt;

forming said background processing mask as a background prefetch processing mask; and

initiating said background processing as background prefetch processing.

2. The method of claim 1, further comprising:

forming said background thread interrupt as a low-priority thread interrupt to perform low-priority background processing using said idle thread; and

issuing said low-priority thread interrupt upon the occurrence of said predetermined event.

3. The method of claim 1, further comprising:

sensing of a cache miss as said predetermined event in said active thread of said plurality of processing threads during processing of said digital signal processor; and

issuing said background thread interrupt from said interrupt register in response to said cache miss.

4. The method of claim 1, further comprising forming said background thread interrupt as a data element of a translation lookaside buffer associated with said digital signal processor.

5. The method of claim 4, further comprising changing said data element of said translation lookaside buffer according to varying operations on said digital signal processor.

6. The method of claim 1, further comprising selecting said idle thread of said subset of said plurality of processing threads to service said background thread interrupt.

7. The method of claim 1, further comprising performing said background processing during interleaved multithreaded operation of said plurality of processing threads.

8. The method of claim 1, further comprising terminating said background processing in said idle thread upon said interrupt register issuing an interrupt having a higher priority than said background processing interrupt.

9. A system to operate in association with a multithreaded digital signal processor to process interrupts, the system comprising:

a multithreaded digital signal processor;

a background thread interrupt to operate as one of a plurality of interrupt types, said background thread interrupt to initiate to initiate a background process using one of a plurality of processing threads of said multithreaded digital signal processor;

an interrupt register to store said background thread interrupt;

a mask register to associate a said background processing mask with at least a subset of said plurality of processing threads;

event sensing instructions to sense a predetermined event in an active thread of said plurality of processing threads during processing of said multithreaded digital signal processor;

interrupt issuing instructions associated with said interrupt register to issue said background thread interrupt from said interrupt register in response to said predetermined event; and

background processing circuitry to initiate background processing using an idle thread of said subset of said plurality of processing threads having an associated background process mask, wherein said multithreaded digital signal processor is operable to support concurrent execution of two or more of said plurality of processing threads;

circuitry and instructions associated with said interrupt register to store said background thread interrupt as a background prefetch interrupt;

circuitry and instructions associated with said mask register to form said background processing mask as a background prefetch processing mask; and

background processing circuitry and instructions to initiate said background processing as background prefetch processing.

10. The system of claim 9, further comprising:

processing instructions and circuitry to form said background thread interrupt as a low-priority thread interrupt to perform low-priority background processing using said subset of said plurality of processing threads; and

issuing instructions associated with said interrupt register for issuing to issue said low-priority thread interrupt upon the occurrence of said predetermined event.

11. The system of claim 9, further comprising:

event sensing circuitry and instructions to sense a cache miss as said predetermined event in said active thread of said plurality of processing threads during processing of said digital signal processor; and

interrupt issuing circuitry and instructions to issue said background thread interrupt from said interrupt register in response to said cache miss.

12. The system of claim 9, further comprising thread interrupt forming instructions to form said background thread interrupt as a data element of a translation lookaside buffer associated with said digital signal processor.

13. The system of claim 12, wherein said thread interrupt forming instructions further comprise instructions to change said data element of said translation lookaside buffer according to varying operations on said digital signal processor.

14. The system of claim 13, further comprising thread selection circuitry and instructions to select said idle thread of said subset of said plurality of processing threads to service said background thread interrupt.

15. The system of claim 9, wherein said processor further comprises processing instructions to perform said background processing during interleaved multithreaded operation of said plurality of processing threads.

16. The system of claim 9, wherein said processor further comprises processing circuitry and instructions to terminate said background processing in said idle thread of said subset of said plurality of processing threads upon said interrupt register issuing an interrupt having a higher priority than said background processing interrupt.

17. A multithreaded digital signal processor to operate in support of a personal electronics device, said multithreaded digital signal processor comprising means for performing background processing, said background processing means comprising:

means for forming a background thread interrupt as one of a plurality of interrupt types, said background thread interrupt for initiating a background process using one of a plurality of processing threads of a multithreaded digital signal processor;

means for storing said background thread interrupt in an interrupt register;

means for forming a background processing mask; and

means for associating said background processing mask with at least a subset of said plurality of processing threads;

means for sensing a predetermined event in an active thread of said plurality of processing threads during processing of said multithreaded digital signal processor;

means for issuing said background thread interrupt from said interrupt register in response to said predetermined event; and

means for initiating background processing using an idle thread of said subset of said plurality of processing threads having an associated background process mask, wherein said multithreaded digital signal processor is operable to support concurrent execution of two or more of said plurality of processing threads;

means for storing said background thread interrupt as a background prefetch interrupt;

means for forming said background processing mask as a background prefetch processing mask; and

means for initiating said background processing as background prefetch processing.

18. The multithreaded digital signal processor of claim 17, further comprising:

means for forming said background thread interrupt as a low-priority thread interrupt for performing low-priority background processing using said idle thread of said subset of said plurality of processing threads; and

means for issuing said low-priority thread interrupt upon the occurrence of said predetermined event.

19. The multithreaded digital signal processor of claim 17, further comprising means for forming said background thread interrupt as a data element of a translation lookaside buffer associated with said multithreaded digital signal processor.

20. The multithreaded digital signal processor of claim 19, further comprising means for changing said data element of said translation lookaside buffer according to varying operations on said multithreaded digital signal processor.

21. The multithreaded digital signal processor of claim 17, further comprising means for selecting said idle thread of said subset of said plurality of processing threads to service said background thread interrupt.

22. The multithreaded digital signal processor of claim 17, further comprising means for performing said background processing during interleaved multithreaded operation of said plurality of processing threads.

23. The multithreaded digital signal processor of claim 17, further comprising means for terminating said background processing in said idle thread of , said subset of said plurality of processing threads upon said interrupt register issuing an interrupt having a higher priority than said background processing interrupt.

24. A non-transitory computer usable medium having computer readable program code means embodied therein to perform background processing in a multithreaded digital signal processor, the computer usable medium comprising:

computer readable program code means for forming a background thread interrupt, said background thread interrupt for initiating a background process using one of a plurality of processing threads of said multithreaded digital signal processor;

computer readable program code means for storing said background thread interrupt in an interrupt register;

computer readable program code means for associating a background processing mask with at least one of said plurality of processing threads;

computer readable program code means for sensing an event in an active thread of said plurality of processing threads during processing of said multithreaded digital signal processor;

computer readable program code means for identifying a subset of said plurality of processing threads of said multithreaded digital signal processor, wherein the subset of said plurality of processing threads is limited to include threads that are eligible to service said background thread interrupt and that are in an idle state;

computer readable program code means for issuing said background thread interrupt from said interrupt register in response to said event;

computer readable program code means for initiating background processing using an idle thread of said subset of said plurality of processing threads, the idle thread having an associated background process mask, wherein said multithreaded digital signal processor is operable to support concurrent execution of two or more of said plurality of processing threads;

computer readable program code means for storing said background thread interrupt as a background prefetch interrupt;

computer readable program code means for forming said background processing mask as a background prefetch processing mask; and

computer readable program code means for initiating said background processing as background prefetch processing.