Light exposure mask and method for manufacturing semiconductor device using the same

• US 7,914,971 B2
• Filed: 08/08/2006
• Issued: 03/29/2011
• Est. Priority Date: 08/12/2005
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Ohnuma, Hideto, Nagai, Masaharu
• Primary Examiner(s): Rosasco; Stephen
• Assistant Examiner(s): JELSMA, JONATHAN G
• Application Number:
  US11/463,147
• Publication Number:
  US 20070037070A1
• Time in Patent Office: 1,694 Days
• Field of Search: 430/5, 430/311
• US Class Current: 430/311
• CPC Class Codes: G03F 1/50 Mask blanks not covered by G03F1/20 - G03F1/34; Preparation thereof
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile

Abstract

The present invention provides a light exposure mask which can form a photoresist layer in a semi-transmissive portion with uniform thickness, and a method for manufacturing a semiconductor device in which the number of photolithography steps (the number of masks) necessary for manufacturing a TFT substrate is reduced by using the light exposure mask. A light exposure mask is used, which includes a transmissive portion, a light shielding portion, and a semi-transmissive portion having a light intensity reduction function where lines and spaces are repeatedly formed, wherein the sum of a line width L of a light shielding material and a space width S between light shielding materials in the semi-transmissive portion satisfies a conditional expression (2n/3)×m≦L+S≦(6n/5)×m when a resolution of a light exposure apparatus is represented by n and a projection magnification is represented by 1/m (m≧1).

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first insulating film over a semiconductor layer;

forming a conductive film over the first insulating film;

forming a first resist pattern over the conductive film, the first resist pattern having a first region and a second region thinner than the first region on a side of the first region by using a light exposure mask including a semi-transmissive portion;

forming a gate electrode having a third region and a fourth region thinner than the third region on a side of the third region by etching the conductive film with the use of the first resist pattern;

injecting an impurity element into the semiconductor layer with the use of the gate electrode as a mask to form a source region and a drain region outside the gate electrode, and injecting the impurity element into the semiconductor layer through the second region of the gate electrode to form a first impurity region and a second impurity region in a region overlapped with the second region of the gate electrode;

forming a second insulating film over the gate electrode;

forming a second resist pattern over the second insulating film, the second resist pattern having a first opening and a second opening shallower than the first opening, by using the light exposure mask including the semi-transmissive portion; and

forming a third opening and a fourth opening in the second insulating film by etching the second insulating film with the use of the second resist pattern, the first opening being overlapped with the third opening, the second opening being overlapped with the fourth opening, and a depth of the third opening being different from a depth of the fourth opening,

wherein the first resist pattern and the second resist pattern are formed by using the light exposure mask in which a sum of a line width L of a light shielding material and a space width S between light shielding materials in the semi-transmissive portion satisfies a conditional expression (n/3)×

m≦

L+S≦

(3n/2)×

m when a resolution of a light exposure apparatus is represented by n and a projection magnification is represented by 1/m (m≧

1).

3. A method for manufacturing a semiconductor device according to claim 1, wherein a relation between n, m, and L satisfies L<

(2n/3)×

m.

5. A method for manufacturing a semiconductor device according to claim 1, wherein each of the first and second impurity regions contains an impurity element imparting n-type or p-type conductivity at a concentration lower than that of each of the source region and the drain region.

2. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first insulating film over a semiconductor layer;

forming a conductive film over the first insulating film;

forming a first resist pattern over the conductive film, the first resist pattern having a first region and a second region thinner than the first region on a side of the first region by using a light exposure mask including a semi-transmissive portion;

forming a gate electrode having a third region and a fourth region thinner than the third region on a side of the third region by etching the conductive film with the use of the first resist pattern;

injecting an impurity element into the semiconductor layer with the use of the gate electrode as a mask to form a source region and a drain region outside the gate electrode, and injecting the impurity element into the semiconductor layer through the second region of the gate electrode to form a first impurity region and a second impurity region in a region overlapped with the second region of the gate electrode;

forming a second insulating film over the gate electrode;

forming a second resist pattern over the second insulating film, the second resist pattern having a first opening and a second opening shallower than the first opening by using the light exposure mask including the semi-transmissive portion; and

forming a third opening and a fourth opening in the second insulating film by etching the second insulating film with the use of the second resist pattern, the first opening being overlapped with the third opening, the second opening being overlapped with the fourth opening, and a depth of the third opening being different from a depth of the fourth opening,

wherein the first resist pattern and the second resist pattern are formed by using the light exposure mask in which a sum of a line width L of a light shielding material and a space width S between light shielding materials in the semi-transmissive portion satisfies a conditional expression (2n/3)×

m≦

L+S≦

(6n/5)×

m when a resolution of a light exposure apparatus is represented by n and a projection magnification is represented by 1/m (m≧

1).

4. A method for manufacturing a semiconductor device according to claim 2, wherein a relation between n, m, and L satisfies L<

(2n/3)×

m.

6. A method for manufacturing a semiconductor device according to claim 2, wherein each of the first and second impurity regions contains an impurity element imparting n-type or p-type conductivity at a concentration lower than that of each of the source region and the drain region.

7. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first insulating film over a semiconductor layer;

forming a conductive film over the first insulating film;

forming a first resist pattern over the conductive film, the first resist pattern having a first region and a second region thinner than the first region on a side of the first region by using a light exposure mask including a semi-transmissive portion;

forming a gate electrode having a third region and a fourth region thinner than the third region on a side of the third region by etching the conductive film with the use of the first resist pattern;

injecting an impurity element into the semiconductor layer with the use of the gate electrode as a mask to form a source region and a drain region outside the gate electrode, and injecting the impurity element into the semiconductor layer through the second region of the gate electrode to form a first impurity region and a second impurity region in a region overlapped with the second region of the gate electrode;

forming a second insulating film over the gate electrode;

forming a second resist pattern over the second insulating film, the second resist pattern having a first opening and a second opening shallower than the first opening by using the light exposure mask including the semi-transmissive portion;

forming a third opening and a fourth opening in the second insulating film by etching the second insulating film with the use of the second resist pattern, the first opening being overlapped with the third opening, the second opening being overlapped with the fourth opening, and a depth of the third opening being different from a depth of the fourth opening; and

forming a first wiring over the third opening and a second wiring over the fourth opening,

wherein the first resist pattern and the second resist pattern are formed by using the light exposure mask in which a sum of a line width L of a light shielding material and a space width S between light shielding materials in the semi-transmissive portion satisfies a conditional expression (n/3)×

m≦

L+S≦

(3n/2)×

m when a resolution of a light exposure apparatus is represented by n and a projection magnification is represented by 1/m (m≧

1).

9. A method for manufacturing a semiconductor device according to claim 7, wherein a relation between n, m, and L satisfies L<

(2n/3)×

m.

11. A method for manufacturing a semiconductor device according to claim 7, wherein each of the first and second impurity regions contains an impurity element imparting n-type or p-type conductivity at a concentration lower than that of each of the source region and the drain region.

8. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first insulating film over a semiconductor layer;

forming a conductive film over the first insulating film;

forming a first resist pattern over the conductive film, the first resist pattern having a first region and a second region thinner than the first region on a side of the first region by using a light exposure mask including a semi-transmissive portion;

forming a gate electrode having a third region and a fourth region thinner than the third region on a side of the third region by etching the conductive film with the use of the first resist pattern;

injecting an impurity element into the semiconductor layer with the use of the gate electrode as a mask to form a source region and a drain region outside the gate electrode, and injecting the impurity element into the semiconductor layer through the second region of the gate electrode to form a first impurity region and a second impurity region in a region overlapped with the second region of the gate electrode;

forming a second insulating film over the gate electrode;

forming a second resist pattern over the second insulating film, the second resist pattern having a first opening and a second opening shallower than the first opening by using the light exposure mask including the semi-transmissive portion;

forming a third opening and a fourth opening in the second insulating film by etching the second insulating film with the use of the second resist pattern, the first opening being overlapped with the third opening, the second opening being overlapped with the fourth opening, and a depth of the third opening being different from a depth of the fourth opening; and

forming a first wiring over the third opening and a second wiring over the fourth opening,

wherein the first resist pattern and the second resist pattern are formed by using the light exposure mask in which a sum of a line width L of a light shielding material and a space width S between light shielding materials in the semi-transmissive portion satisfies a conditional expression (2n/3)×

m≦

L+S≦

(6n/5)×

m when a resolution of a light exposure apparatus is represented by n and a projection magnification is represented by 1/m (m≧

1).

10. A method for manufacturing a semiconductor device according to claim 8, wherein a relation between n, m, and L satisfies L<

(2n/3)×

m.

12. A method for manufacturing a semiconductor device according to claim 8, wherein each of the first and second impurity regions contains an impurity element imparting n-type or p-type conductivity at a concentration lower than that of each of the source region and the drain region.