Method of manufacturing layered chip package

• US 7,915,083 B1
• Filed: 10/28/2009
• Issued: 03/29/2011
• Est. Priority Date: 10/28/2009
• Status: Active Grant

• Current Assignee: Headway Technologies Incorporated, SAE Magnetics Limited (TDK Corporation)
• Original Assignee: Headway Technologies Incorporated, SAE Magnetics Limited (TDK Corporation)
• Inventors: Ito, Hiroyuki, Ikejima, Hiroshi, Iijima, Atsushi, Sasaki, Yoshitaka
• Primary Examiner(s): Richards; N Drew
• Assistant Examiner(s): DIALLO, MAMADOU L
• Application Number:
  US12/588,806
• Time in Patent Office: 517 Days
• Field of Search: 257/E21.614, 257/686, 257/E25.006, 257/E25.013, 257/E25.018, 257/E25.027, 257/E23.085, 257/E21.569, 257/777, 438/109, 438/113, 438/612
• US Class Current: 438/109
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05541 Structure
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/25 of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor

Abstract

A layered chip package includes a main body, and wiring disposed on at least one side surface of the main body. The main body has: a main part having a top surface and a bottom surface and including a plurality of layer portions stacked; and a plurality of terminals arranged on at least one of the top and bottom surfaces of the main part and electrically connected to the wiring. A manufacturing method for the layered chip package includes: fabricating a plurality of first layered substructures each including a plurality of pre-separation main bodies arrayed; fabricating a second layered substructure by stacking the first layered substructures; cutting the second layered substructure into a block in which a plurality of pre-separation main bodies are arrayed in two directions; forming the wiring simultaneously for the plurality of pre-separation main bodies included in the block; and separating the pre-separation main bodies from each other.

Claims

1. A method of manufacturing a plurality of layered chip packages, each of the layered chip packages comprising:

a main body having a top surface, a bottom surface, and four side surfaces; and

wiring disposed on at least one of the side surfaces of the main body, wherein;

the main body has a main part and a plurality of terminals, the main part having a top surface and a bottom surface and including a plurality of layer portions stacked, the plurality of terminals being arranged on at least one of the top and bottom surfaces of the main part and electrically connected to the wiring;

each of the plurality of layer portions includes a semiconductor chip;

at least one of the plurality of layer portions further includes a plurality of electrodes that are electrically connected to the semiconductor chip and that each have an end face located at the at least one of the side surfaces of the main body on which the wiring is disposed; and

the wiring is electrically connected to the end faces of the plurality of electrodes,

the method comprising the steps of;

fabricating a plurality of substructures each of which includes a plurality of preliminary layer portions arrayed, each of the preliminary layer portions being intended to be made into any one of the layer portions included in the main part, the substructures being intended to be cut later at a position of a boundary between every adjacent preliminary layer portions;

fabricating a plurality of first layered substructures by using the plurality of substructures, each of the first layered substructures including a plurality of substructures stacked; and

producing the plurality of layered chip packages by using the plurality of first layered substructures, wherein;

each of the first layered substructures includes a plurality of pre-separation main bodies that are arrayed and intended to be separated from each other later into the individual main bodies; and

the step of producing the plurality of layered chip packages includes the steps of;

fabricating a second layered substructure by stacking the plurality of first layered substructures and bonding every two adjacent first layered substructures to each other;

cutting the second layered substructure into at least one block in which a plurality of pre-separation main bodies are arrayed both in a direction of stacking of the first layered substructures and in a direction orthogonal thereto;

forming the wiring simultaneously for the plurality of pre-separation main bodies included in the at least one block; and

separating the plurality of pre-separation main bodies each provided with the wiring from each other so as to form the plurality of layered chip packages.

2. The method of manufacturing the layered chip packages according to claim 1, wherein:

the semiconductor chip has four side surfaces;

each of the plurality of layer portions further includes an insulating portion that covers at least one of the four side surfaces of the semiconductor chip; and

the insulating portion has at least one end face that is located at the at least one of the side surfaces of the main body on which the wiring is disposed.

3. The method of manufacturing the layered chip packages according to claim 1, wherein the plurality of terminals are arranged on the top surface and the bottom surface of the main part.

4. The method of manufacturing the layered chip packages according to claim 1, wherein the at least one block is two or more blocks, and, in the step of forming the wiring, the two or more blocks are arrayed with all the pre-separation main bodies included in the two or more blocks arranged so that their respective surfaces on which the wiring is to be formed face toward an identical direction, and then the wiring is formed simultaneously for all the pre-separation main bodies included in the two or more blocks.