Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys
First Claim
1. A method for fabricating a junction field effect transistor, the method comprising:
- forming a first impurity region of a first conductivity type in a semiconductor substrate;
forming a second impurity region of a first conductivity type in the semiconductor substrate;
forming a channel region of the first conductivity type between the first and second impurity regions, wherein the channel region has a maximum length of less than 100 nm;
forming a gate electrode region of a second conductivity type such that the gate electrode region overlays the semiconductor substrate;
diffusing impurities of the second conductivity type from the gate electrode region into the semiconductor substrate to form a gate region that is substantially aligned with the gate electrode region.
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Abstract
This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices.
25 Citations
18 Claims
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1. A method for fabricating a junction field effect transistor, the method comprising:
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forming a first impurity region of a first conductivity type in a semiconductor substrate; forming a second impurity region of a first conductivity type in the semiconductor substrate; forming a channel region of the first conductivity type between the first and second impurity regions, wherein the channel region has a maximum length of less than 100 nm; forming a gate electrode region of a second conductivity type such that the gate electrode region overlays the semiconductor substrate; diffusing impurities of the second conductivity type from the gate electrode region into the semiconductor substrate to form a gate region that is substantially aligned with the gate electrode region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method for fabricating one or more semiconductor devices comprising the steps of:
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building one or more isolation regions in a semiconductor substrate of a first conductivity type, the isolation regions being filled with dielectric material; doping one or more regions in the semiconductor substrate to form one or more well regions of the first conductivity type and one or more well regions of the second conductivity type opposite to the first conductivity type; forming one or more channel regions in the one or more well regions wherein each channel region is of a conductivity type opposite to the conductivity type of the corresponding well region; depositing a first semiconductor layer on the semiconductor substrate; doping the first semiconductor layer selectively above each well region to dope one or more drain contact regions, one or more source contact regions, one or more gate electrode regions, and one or more well contact regions;
wherein each drain and source regions are doped with a conductivity type opposite to the conductivity type of the corresponding well region;
wherein each gate electrode and well contact regions are doped with the conductivity type of the corresponding well region;depositing a first dielectric layer on top of the first semiconductor layer to form a blocking layer; masking and etching the first semiconductor layer for forming one or more drain contact regions, one or more source contact regions, one or more gate electrode regions, and one or more well contact regions; forming one or more first source link regions and one or more first drain link regions in the one or more well regions by ion implantation; wherein each first source link region connects between a region immediately underneath a source contact region and a channel region; wherein each first drain link region connects between a region immediately underneath a drain contact region and a channel region; and wherein each first source link region and each first drain link region are implanted with a conductivity type opposite to the conductivity type of the corresponding well region; annealing the semiconductor substrate with the first semiconductor layers and the first dielectric layer; filling up the regions etched away in the first semiconductor layer during the masking and etching step with dielectric material for forming a planar surface; removing the blocking layer non-selectively; forming silicide on top of the first semiconductor layer selectively; depositing a second dielectric layer on the semiconductor substrate and etching to form contact holes; and depositing and etching one or more metal layers on the semiconductor substrate for forming interconnections. - View Dependent Claims (16, 17, 18)
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Specification