Chip structure and process for forming the same

• US 7,915,157 B2
• Filed: 02/02/2008
• Issued: 03/29/2011
• Est. Priority Date: 12/21/1998
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan, Huang, Ching-Cheng
• Primary Examiner(s): Ghyka; Alexander G
• Assistant Examiner(s): MUSTAPHA, ABDULFATTAH B
• Application Number:
  US12/025,001
• Publication Number:
  US 20080124918A1
• Time in Patent Office: 1,151 Days
• Field of Search: 438/584, 438/597, 438/604, 438/622, 438/623, 257/E21.091, 257/E21.169, 257/E21.459
• US Class Current: 438/597
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 23/60 : Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 27/0251 : for MOS devices
• CPC Class Codes: H01L 27/0676 : comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 : including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: Y10T 29/49124 : On flat or curved insulated base, e.g., printed circuit, etc.
• CPC Class Codes: Y10T 29/49204 : Contact or terminal manufacturing

Abstract

A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.

Claims

1. A method for fabricating a chip, comprising:

providing a wafer comprising a silicon substrate, a transistor in or on said silicon substrate, a first copper layer over said silicon substrate, a second copper layer over said first copper layer and said silicon substrate, a dielectric layer between said first and second copper layers, a copper plug in said dielectric layer and between said first and second copper layers, wherein said copper plug connects said first and second copper layers, a conductive pad over said silicon substrate, a passivation layer over said first and second copper layers and said dielectric layer, wherein said passivation layer comprises a nitride, wherein a first opening in said passivation layer is over a contact point of said conductive pad, and said contact point is at a bottom of said first opening, and a first polymer layer on said passivation layer, wherein a second opening in said first polymer layer is over said contact point, wherein said first polymer layer has a thickness between 1 and 100 micrometers; and

forming a metallization structure over said wafer, on a top surface of said first polymer layer and on said contact point, wherein said metallization structure is connected to said contact point through said second opening, wherein said forming said metallization structure comprises forming a metal layer on said top surface of said first polymer layer, on a sidewall of said second opening and on said contact point, followed by forming a photoresist layer on said metal layer, wherein a third opening in said photoresist layer exposes a region of said metal layer, followed by electroplating a third copper layer on said region, followed by removing said photoresist layer, followed by removing said metal layer not under said third copper layer.

2. The method of claim 1, wherein said first polymer layer comprises polyimide.

3. The method of claim 1, wherein said first polymer layer comprises benzocyclobutene (BCB).

4. The method of claim 1, wherein said metal layer comprises titanium.

5. The method of claim 1, wherein said metal layer comprises a titanium-tungsten alloy.

6. The method of claim 1 further comprising forming a second polymer layer on said metallization structure.

7. The method of claim 6, wherein said second polymer layer comprises polyimide.

8. The method of claim 1, wherein said forming said metal layer comprises a sputtering process.

9. The method of claim 1, wherein said providing said first polymer layer comprises a spin-coating process.

10. The method of claim 1, wherein said passivation layer further comprises an oxide.

11. A method for fabricating a chip, comprising:

providing a wafer comprising a silicon substrate, a transistor in or on said silicon substrate, a first copper layer over said silicon substrate, a second copper layer over said first copper layer and said silicon substrate, a dielectric layer between said first and second copper layers, a copper plug in said dielectric layer and between said first and second copper layers, wherein said copper plug connects said first and second copper layers, a first conductive pad over said silicon substrate, a second conductive pad over said silicon substrate, a passivation layer over said first and second copper layers and said dielectric layer, wherein said passivation layer comprises a nitride, wherein a first opening in said passivation layer is over a first contact point of said first conductive pad, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of said second conductive pad, and said second contact point is at a bottom of said second opening, and a first polymer layer on said passivation layer, wherein a third opening in said first polymer layer is over said first contact point, and wherein a fourth opening in said first polymer layer is over said second contact point, wherein said first polymer layer has a thickness between 1 and 100 micrometers; and

forming a metallization structure over said wafer, on a top surface of said first polymer layer and on said first and second contact points, wherein said first contact point is connected to said second contact point through said metallization structure, wherein said forming said metallization structure comprises forming a metal layer on said top surface of said first polymer layer, on sidewalls of said third and fourth openings and on said first and second contact points, wherein said forming said metal layer comprises a sputtering process, followed by forming a photoresist layer on said metal layer, wherein a fifth opening in said photoresist layer exposes a region of said metal layer, followed by electroplating a third copper layer on said region, followed by removing said photoresist layer, followed by removing said metal layer not under said third copper layer.

12. The method of claim 11, wherein said first polymer layer comprises polyimide.

13. The method of claim 11, wherein said first polymer layer comprises benzocyclobutene (BCB).

14. The method of claim 11, wherein said metal layer comprises titanium.

15. The method of claim 11, wherein said metal layer comprises a titanium-tungsten alloy.

16. The method of claim 11 further comprising forming a second polymer layer on said metallization structure.

17. The method of claim 16, wherein said second polymer layer comprises polyimide.

18. The method of claim 11, wherein providing said first polymer layer comprises a spin-coating process.

19. The method of claim 11, wherein said passivation layer further comprises an oxide.

20. A method for fabricating a chip, comprising:

providing a silicon substrate, a transistor in or on said silicon substrate, a first copper layer over said silicon substrate, a second copper layer over said first copper layer and said silicon substrate, a dielectric layer between said first and second copper layers, a copper plug in said dielectric layer and between said first and second copper layers, wherein said copper plug connects said first and second copper layers, a conductive pad over said silicon substrate, and a passivation layer over said silicon substrate, said first and second copper layers and said dielectric layer, wherein said passivation layer comprises a nitride, wherein a first opening in said passivation layer is over a contact point of said conductive pad, and said contact point is at a bottom of said first opening, wherein said first opening has a width between 0.5 and 20 micrometers;

forming a metal layer over a top surface of said passivation layer, on a sidewall of said first opening and on said contact point;

forming a photoresist layer on said metal layer, wherein a second opening in said photoresist layer exposes a region of said metal layer;

electroplating a gold layer over said region;

removing said photoresist layer; and

removing said metal layer not under said gold layer.

21. The method of claim 20, wherein said passivation layer further comprises an oxide.

22. The method of claim 20, wherein said forming said metal layer comprises forming a titanium-containing layer over said top surface of said passivation layer, on said sidewall of said first opening and on said contact point.

23. The method of claim 20, wherein said forming said metal layer comprises a sputtering process.

24. A method for fabricating a chip, comprising:

providing a silicon substrate, a transistor in or on said silicon substrate, a first copper layer over said silicon substrate, a second copper layer over said first copper layer and said silicon substrate, a dielectric layer between said first and second copper layers, a copper plug in said dielectric layer and between said first and second copper layers, wherein said copper plug connects said first and second copper layers, a conductive pad over said silicon substrate, and a passivation layer over said silicon substrate, said first and second copper layers and said dielectric layer, wherein said passivation layer comprises a nitride, wherein a first opening in said passivation layer is over a first contact point of said conductive pad, and said first contact point is at a bottom of said first opening;

forming a first metal interconnect over said passivation layer and on said first contact point, wherein said first metal interconnect is connected to said first contact point through said first opening, wherein said forming said first metal interconnect comprises forming a first metal layer, followed by forming a first photoresist layer on said first metal layer, wherein a second opening in said first photoresist layer exposes a first region of said first metal layer, followed by electroplating a third copper layer on said first region, followed by removing said first photoresist layer, followed by removing said first metal layer not under said third copper layer;

forming a polymer layer over said first metal interconnect and said passivation layer, wherein a third opening in said polymer layer is over a second contact point of said first metal interconnect, wherein said second contact point is connected to said first contact point through said first metal interconnect; and

forming a second metal interconnect on said second contact point and said polymer layer, wherein said second metal interconnect is connected to said second contact point through said third opening, wherein said forming said second metal interconnect comprises forming a second metal layer, followed by forming a second photoresist layer on said second metal layer, wherein a fourth opening in said second photoresist layer exposes a second region of said second metal layer, followed by forming a fourth copper layer on said second region, followed by removing said second photoresist layer, followed by removing said second metal layer not under said fourth copper layer.

25. The method of claim 24, wherein said passivation layer further comprises an oxide.

26. The method of claim 24, wherein said forming said first metal layer comprises forming a titanium-containing layer.

27. The method of claim 24, wherein said forming said first metal layer comprises a sputtering process.

28. The method of claim 24, wherein said forming said second metal layer comprises forming a titanium-containing layer.