Post passivation interconnection schemes on top of IC chip
First Claim
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1. A method for fabricating a chip, comprising:
- providing a silicon substrate and a first interconnecting structure over said silicon substrate, wherein said first interconnecting structure is formed by a process comprising a damascene process, an electroplating process and a CMP process; and
forming a ground interconnect over said silicon substrate, wherein said forming said ground interconnect comprises forming a first metal layer, followed by forming a patterned photoresist layer, followed by electroplating a second metal layer, followed by removing said patterned photoresist layer, followed by etching said first metal layer.
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Abstract
A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
187 Citations
35 Claims
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1. A method for fabricating a chip, comprising:
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providing a silicon substrate and a first interconnecting structure over said silicon substrate, wherein said first interconnecting structure is formed by a process comprising a damascene process, an electroplating process and a CMP process; and forming a ground interconnect over said silicon substrate, wherein said forming said ground interconnect comprises forming a first metal layer, followed by forming a patterned photoresist layer, followed by electroplating a second metal layer, followed by removing said patterned photoresist layer, followed by etching said first metal layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 18, 19, 20, 28)
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9. A method for fabricating a chip, comprising:
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providing a silicon substrate, a first internal circuit in or on said silicon substrate, a second internal circuit in or on said silicon substrate, a dielectric layer over said silicon substrate, a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said first internal circuit, a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said second internal circuit, and a passivation layer over said dielectric layer; and forming a ground interconnect and a polymer layer over said passivation layer, wherein said polymer layer comprises a portion over said ground interconnect, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said ground interconnect and said second interconnecting structure, wherein said forming said ground interconnect comprises forming a first metal layer, followed by forming a patterned photoresist layer, followed by electroplating a second metal layer, followed by removing said patterned photoresist layer, followed by etching said first metal layer. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17)
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21. A method for fabricating a chip, comprising:
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providing a silicon substrate, a dielectric layer over said silicon substrate, an interconnecting structure in said dielectric layer and over said silicon substrate, wherein said interconnecting structure is formed by a process comprising a damascene process, an electroplating process and a CMP process, and a passivation layer over said dielectric layer and over said silicon substrate; and forming a ground interconnect over said passivation layer and over said silicon substrate, wherein said ground interconnect is connected to said interconnecting structure through a via in said passivation layer, wherein said forming said ground interconnect comprises forming a first metal layer, followed by forming a patterned photoresist layer, followed by electroplating a second metal layer, followed by removing said patterned photoresist layer, followed by etching said first metal layer. - View Dependent Claims (22, 23, 24, 25, 26, 27)
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29. A method for fabricating a chip, comprising:
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providing a silicon substrate, a dielectric layer over said silicon substrate, and an interconnecting structure in said dielectric layer and over said silicon substrate, wherein said interconnecting structure is formed by a process comprising a damascene process, an electroplating process and a CMP process; and forming an inductor over said silicon substrate, wherein said forming said inductor comprises forming a first metal layer, followed by forming a patterned photoresist layer, followed by electroplating a second metal layer, followed by removing said patterned photoresist layer, followed by etching said first metal layer. - View Dependent Claims (30, 31, 32)
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33. A method for fabricating a chip, comprising:
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providing a silicon substrate, a dielectric layer over said silicon substrate, a first interconnecting structure over said silicon substrate and in said dielectric layer, a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first and second interconnecting structures are formed by a process comprising a damascene process, an electroplating process and a CMP process, and a separating layer over said dielectric layer; and forming a ground interconnect over said separating layer, wherein said first interconnecting structure is connected to said second interconnecting structure through said ground interconnect, wherein said forming said ground interconnect comprises forming a first metal layer, followed by forming a patterned photoresist layer, followed by electroplating a second metal layer, followed by removing said patterned photoresist layer, followed by etching said first metal layer. - View Dependent Claims (34, 35)
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Specification