Method for forming doped polysilicon via connecting polysilicon layers

• US 7,915,164 B2
• Filed: 10/04/2010
• Issued: 03/29/2011
• Est. Priority Date: 09/29/2004
• Status: Expired due to Fees

• Current Assignee: Woden Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Nallamothu, Sucheta, Mahajani, Maitreyee, Kumar, Tanmay, Konevecki, Michael W., Raghuram, Usha, Walker, Andrew J.
• Primary Examiner(s): Vu; David
• Assistant Examiner(s): Taylor; Earl N
• Application Number:
  US12/897,696
• Publication Number:
  US 20110021019A1
• Time in Patent Office: 176 Days
• Field of Search: 438/368, 438/672, 438/675, 438/684, 257/E21.627, 257/E21.585, 257/E21.641, 257/E21.677
• US Class Current: 438/672
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.

Claims

1. A method for forming a via structure to connect device levels in a monolithic three dimensional array, the method comprising:

providing a substrate;

forming a first device level of thin film transistors at a first height above the substrate, the first device level comprising a first polysilicon layer, the first polysilicon layer is a gate electrode of a thin film transistor of the first device level of thin film transistors;

forming a polysilicon via above the first polysilicon layer, a bottom surface of the polysilicon via is in contact with the first polysilicon layer; and

forming a second device level of thin film transistors at a second height above the substrate, wherein the second height is above the first height, the second device level comprising a second polysilicon layer,

wherein the second polysilicon layer is above the polysilicon via, and a top surface of the polysilicon via is in contact with the second polysilicon layer.

2. The method of claim 1, wherein the monolithic three dimensional array is an array of memory cells.

3. The method of claim 2, wherein the memory cells comprise charge storage memory cells.

4. The method of claim 3, wherein the charge storage memory cells comprise SONOS-type memory cells.

5. The method of claim 3, wherein the charge storage memory cells comprise floating gate memory cells.

6. The method of claim 1, wherein the step of forming a polysilicon via comprises:

forming a layer of dielectric material;

etching a void in the layer of dielectric material;

filling the void with in situ doped polysilicon; and

planarizing the dielectric material and the in situ doped polysilicon to form a shared top surface.

7. The method of claim 1, wherein the substrate comprises monocrystalline silicon.