Semiconductor device

• US 7,915,617 B2
• Filed: 07/03/2006
• Issued: 03/29/2011
• Est. Priority Date: 07/04/2005
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ogura, Tsuneo, Omura, Ichiro
• Primary Examiner(s): Andújar; Leonardo
• Assistant Examiner(s): HARRISTON, WILLIAM A
• Application Number:
  US11/478,623
• Publication Number:
  US 20070007537A1
• Time in Patent Office: 1,730 Days
• Field of Search: 257/77, 257/288, 257/192, 257/330, 257/341, 257/401, 257/E29.297, 438/268, 438/275, 438/981
• US Class Current: 257/77
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

A semiconductor device comprises: a first semiconductor layer of silicon carbide of a first conductivity type; a second semiconductor layer of silicon carbide of a second conductivity type selectively provided on the first semiconductor layer; a main electrode layer of silicon carbide of the first conductivity type selectively provided on the second semiconductor layer; a gate insulating film provided on the second semiconductor layer; a gate electrode formed on the gate insulating film; and a third semiconductor layer of the first conductivity type intervening a current path which is formed between the main electrode layer and the first semiconductor layer when an ON voltage is applied to the gate electrode. The third semiconductor layer is selectively provided on the first semiconductor layer and is adjacent to the second semiconductor layer. A doping density of the third semiconductor layer is higher than a doping density of the first semiconductor layer.

Claims

1. A semiconductor device comprising:

a first semiconductor layer of silicon carbide of a first conductivity type;

a second semiconductor layer of silicon carbide of a second conductivity type selectively provided on the first semiconductor layer;

a main electrode layer of silicon carbide of the first conductivity type selectively provided on the second semiconductor layer;

a gate insulating film provided on the second semiconductor layer;

a gate electrode formed on the gate insulating film; and

a third semiconductor layer of the first conductivity type intervening a current path which is formed between the main electrode layer and the first semiconductor layer when an ON voltage is applied to the gate electrode,

the third semiconductor layer being selectively provided on the first semiconductor layer and being adjacent to the second semiconductor layer,

the current path includes a part of the second semiconductor layer, the part being provided between the main electrode layer and the third semiconductor layer, and the part being covered by the gate insulating film, and

a doping density of the third semiconductor layer being higher than a doping density of the first semiconductor layer;

and further comprising an accumulation channel layer of silicon carbide of the first conductivity type selectively provided between the gate insulating film and the second semiconductor layer and having a lower impurity concentration than the main electrode layer, and

the current path includes the accumulation channel layer and an inversion channel layer, the accumulation channel layer and the inversion channel layer being connected in series, and the inversion channel layer being formed in a semiconductor of the second conductivity type when the ON voltage is applied to the gate electrode.

2. A semiconductor device according to claim 1, wherein the second semiconductor layer of silicon carbide of the second conductivity type is formed by epitaxial growth.

3. A semiconductor device according to claim 1, wherein the third semiconductor layer is formed by diffusing an impurity of the first conductivity type from a surface of the second semiconductor layer.

4. A semiconductor device according to claim 1, further comprising a second main electrode layer of a second conductivity type provided below the first semiconductor layer, the second main electrode layer having higher impurity concentration than the first semiconductor layer.

5. A semiconductor device according to claim 4, wherein the second main electrode layer of the second conductivity type is a layer formed by an epitaxial growth or by diffusing an impurity of the second conductivity type on a surface of the first semiconductor layer.

17. A semiconductor device according to claim 1, wherein the semiconductor of the second conductivity type is provided in the accumulation channel layer or adjoining the accumulation channel layer between the gate insulating film and the second semiconductor layer.

18. A semiconductor device according to claim 1, wherein the semiconductor of the second conductivity type is the part of the second semiconductor layer.

6. A semiconductor device comprising:

a first semiconductor layer of silicon carbide of a first conductivity type;

a second semiconductor layer of silicon carbide of a second conductivity type selectively provided on the first semiconductor layer;

a main electrode layer of silicon carbide of the first conductivity type selectively provided on the second semiconductor layer;

a gate insulating film;

a gate electrode adjoining the gate insulating film; and

an accumulation channel layer of silicon carbide of the first conductivity type provided between the second semiconductor layer and the gate insulating film, the accumulation channel layer having a lower impurity concentration than the main electrode layer,

the accumulation channel layer intervening a current path which is formed between the main electrode layer and the first semiconductor layer when an ON voltage is applied to the gate electrode, and

the current path includes the accumulation channel layer and an inversion channel layer, the accumulation channel layer and the inversion channel layer being connected in series, and the inversion channel layer being formed in a semiconductor layer of the second conductivity type when the ON voltage is applied to the gate electrode,

wherein a thickness of the accumulation channel layer is smaller than a thickness of the second semiconductor layer in a stacking direction of stacking the second semiconductor layer and the gate insulating film.

7. A semiconductor device according to claim 6, wherein the semiconductor layer of the second conductivity type is provided in the accumulation channel layer or adjoining the accumulation channel layer between the gate insulating film and the second semiconductor layer.

8. A semiconductor device according to claim 6, further comprising a second main electrode layer of a second conductivity type provided below the first semiconductor layer, the second main electrode layer having higher impurity concentration than the first semiconductor layer.

9. A semiconductor device according to claim 8, wherein the second main electrode layer of the second conductivity type is a layer formed by an epitaxial growth or by diffusing an impurity of the second conductivity type on a surface of the first semiconductor layer.

19. A semiconductor device according to claim 6, wherein the semiconductor layer of the second conductivity type is the part of the second semiconductor layer, and the part is adjacent to the gate insulating film.

20. A semiconductor device according to claim 6, further comprising a first main electrode adjoining the main electrode layer and a second main electrode electrically connected with the first semiconductor layer.

10. A semiconductor device comprising:

a first semiconductor layer of silicon carbide of a first conductivity type;

a second semiconductor layer of silicon carbide of a second conductivity type selectively provided on the first semiconductor layer;

a main electrode layer of silicon carbide of the first conductivity type selectively provided on the second semiconductor layer;

a gate insulating film;

a gate electrode adjoining the gate insulating film; and

an accumulation channel layer of silicon carbide of the first conductivity type provided between the second semiconductor layer and the gate insulating film, the accumulation channel layer having a lower impurity concentration than the main electrode layer,

the accumulation channel layer intervening a current path which is formed between the main electrode layer and the first semiconductor layer when an ON voltage is applied to the gate electrode, and

the current path includes the accumulation channel layer and an inversion channel layer, the accumulation channel layer and the inversion channel layer being connected in series, and the inversion channel layer being formed in a semiconductor layer of the second conductivity type when the ON voltage is applied to the gate electrode,

wherein the gate insulating film is provided on an inner wall surface of a trench which penetrates the main electrode layer and the second semiconductor layer and reaches the first semiconductor layer, and

the gate electrode is surrounded by the gate insulating film and is packed inside the trench.

11. A semiconductor device comprising:

a first semiconductor layer of silicon carbide of a first conductivity type;

a main electrode layer of silicon carbide of the first conductivity type provided on the first semiconductor layer;

a main electrode provided on the main electrode layer;

a trench penetrating the main electrode layer and extending in the first semiconductor layer;

a gate insulating film provided on an inner wall surface of the trench;

a gate electrode surrounded by the gate insulating film and packed inside the trench;

an accumulation channel layer of silicon carbide of the first conductivity type provided between the gate insulating film and the first semiconductor layer and having a lower impurity concentration than the main electrode layer; and

a fourth semiconductor layer of a second conductivity type provided in the first semiconductor layer, the fourth semiconductor layer being spaced apart from and opposed to the accumulation channel layer, and the fourth semiconductor layer being electrically connected with the main electrode.

12. A semiconductor device according to claim 11, wherein

a current path being formed in the accumulation channel layer when an ON voltage is applied to the gate electrode, and

the accumulation channel layer being depleted when the ON voltage is not applied to the gate electrode.

13. A semiconductor device according to claim 11, further comprising a second main electrode layer of the first conductivity type provided below the first semiconductor layer, the second main electrode layer having higher impurity concentration than the first semiconductor layer.

14. A semiconductor device according to claim 11, further comprising a second main electrode layer of a second conductivity type provided below the first semiconductor layer, the second main electrode layer having higher impurity concentration than the first semiconductor layer.

15. A semiconductor device according to claim 14, wherein the second main electrode layer of the second conductivity type is a layer formed by an epitaxial growth or by diffusing an impurity of the second conductivity type on a surface of the first semiconductor layer.

16. A semiconductor device according to claim 11, wherein a spacing between the accumulation channel layer and the forth semiconductor layer opposing to the accumulation channel layer is not greater than 2 micrometers.