Integrated circuits having a contact region and methods for manufacturing the same

• US 7,915,667 B2
• Filed: 06/11/2008
• Issued: 03/29/2011
• Est. Priority Date: 06/11/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Beug, Florian, Riedel, Stephan, Manger, Dirk, Specht, Michael, Knoefler, Roman, Hofmann, Franz
• Primary Examiner(s): Smith; Zandra
• Assistant Examiner(s): Joy; Jeremy J
• Application Number:
  US12/137,388
• Publication Number:
  US 20090309152A1
• Time in Patent Office: 1,021 Days
• Field of Search: 257/314, 257/324, 257/E21.409, 257/E29.309, 257/206, 257/211, 257/390, 257E21613-E21614, 257/E21.656, 257E21679-E2168, 438/257
• US Class Current: 257/324
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.

Claims

1. An integrated circuit comprising a memory cell arrangement, the memory cell arrangement comprising:

a fin structure extending in a first direction, the fin structure comprising;

a first memory cell structure comprising a plurality of first active regions of a first plurality of memory cells coupled with each other in serial connection in the first direction;

a second memory cell structure comprising a plurality of second active regions of a second plurality of memory cells coupled with each other in serial connection in the first direction, wherein the second memory cell structure is disposed above the first memory cell structure;

a memory cell contact structure configured to electrically couple the first memory cell structure and the second memory cell structure, wherein the memory cell contact structure has a staircase structure, a first step of which is configured to electrically contact the first memory cell structure, and a second step of which is configured to electrically contact the second memory cell structure; and

wherein the first step and the second step each comprises a first doped region doped with doping atoms of a first conductivity type, wherein the memory cell contact structure further comprises second doped regions doped with doping atoms of a second conductivity type, wherein the second conductivity type is different from the first conductivity type, wherein the second doped regions are disposed next to the first doped regions in the first direction.

2. The integrated circuit of claim 1, further comprising:

a plurality of charge storage layer structures disposed adjacent at least one sidewall of the fin structure covering at least a portion of the first active regions and at least a portion of the second active regions.

3. The integrated circuit of claim 2, wherein each charge storage layer structure comprises a structure selected from the group consisting of:

a floating gate layer structure;

a nanocrystalline type layer structure comprising nanocrystals embedded in a dielectric, the nanocrystals being configured to store electrical charges; and

a charge trapping layer structure.

4. The integrated circuit of claim 1, further comprising:

a switch arrangement comprising switches configured to individually select the memory cells of the first and second plurality of memory cells.

5. The integrated circuit of claim 4, wherein the switches comprise transistors.

6. The integrated circuit of claim 1, wherein the memory cell contact structure comprises a plurality of contact holes, wherein each contact hole is coupled with a respective step of the staircase structure.

7. The integrated circuit of claim 1, further comprising:

a bit line coupled with the memory cell contact structure.

8. An integrated circuit comprising a memory cell arrangement, the memory cell arrangement comprising:

a fin structure, comprising;

a first memory cell structure having at least one first active region of at least one first memory cell;

a second memory cell structure having at least one second active region of at least one second memory cell, wherein the second memory cell structure is disposed above the first memory cell structure;

a memory cell contact structure configured to electrically couple the first memory cell structure and the second memory cell structure, wherein the memory cell contact structure has a staircase structure, a first step of which is configured to electrically contact the first memory cell structure, and a second step of which is configured to electrically contact the second memory cell structure; and

wherein the first step and the second step each comprise a first doped region doped with doping atoms of a first conductivity type, wherein the memory cell contact structure further comprises second doped regions doped with doping atoms of a second conductivity type, wherein the second conductivity type is different from the first conductivity type, wherein the second doped regions are disposed next to the first doped region in a first direction.

9. The integrated circuit of claim 8, further comprising:

a plurality of charge storage layer structures disposed adjacent at least one sidewall of the fin structure covering at least a portion of the at least one first active region and at least a portion of the at least one second active region.

10. The integrated circuit of claim 8, further comprising:

a switch arrangement comprising switches configured to individually select memory cells.

11. The integrated circuit of claim 10, wherein the switches a comprise transistors.

12. The integrated circuit of claim 8, wherein the memory cell contact structure comprises a plurality of contact holes, wherein each contact hole is coupled with a respective step of the staircase structure.

13. The integrated circuit of claim 8, further comprising:

a bit line coupled with the memory cell contact structure.

14. An integrated circuit comprising a memory cell arrangement, the memory cell arrangement comprising:

a substrate;

a fin structure disposed above the substrate, the fin structure comprising;

a memory cell region comprising a plurality of memory cell structures being disposed above one another, each memory cell structure comprising an active region of a respective memory cell; and

a memory cell contacting region configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region comprises a plurality of contact regions which are at least partially displaced with respect to each other in a direction parallel to a main processing surface of the substrate; and

wherein each of the plurality of contact regions comprises a first doped region doped with doping atoms of a first conductivity type, wherein each of the plurality of contact regions further comprises second doped regions doped with doping atoms of a second conductivity type, wherein the second conductivity type is different from the first conductivity type, wherein the second doped regions are disposed next to the first doped region in a first direction.

15. The integrated circuit of claim 14, wherein the memory cell contacting region further comprises contact holes arranged substantially perpendicular to a main processing surface of the substrate, wherein each contact hole is configured to contact a respective one of the contact regions.

16. The integrated circuit of claim 14, further comprising a bit line coupled with the memory cell contacting region.

17. The integrated circuit of claim 14, wherein each contact region comprises a first doped region doped with doping atoms of a first conductivity type.

18. The integrated circuit of claim 14, wherein the contact regions are displaced with respect to each other in a direction perpendicular to the main processing surface of the substrate.

19. A method for manufacturing an integrated circuit comprising a memory cell arrangement, the method comprising:

forming a fin structure;

forming a memory cell region in the fin structure, the memory cell region comprising a plurality of memory cell structures disposed above one another, each memory cell structure comprising an active region of a respective memory cell; and

forming a memory cell contacting region configured to electrically contact each of the memory cell structures, such that the memory cell contacting region comprises a plurality of contact regions which are at least partially displaced with respect to each other in a direction parallel to a main processing surface of the substrate, wherein each of the plurality of contact regions comprises a first doped region doped with doping atoms of a first conductivity type, wherein each of the plurality of contact regions further comprises second doped regions doped with doping atoms of a second conductivity type, wherein the second conductivity type is different from the first conductivity type, wherein the second doped regions are disposed next to the first doped region in a first direction.

20. A method for manufacturing an integrated circuit comprising a memory cell arrangement, the method comprising:

forming a fin structure such that the fin structure comprises a first memory cell structure having at least one first active region of at least one first memory cell in the fin structure, and a second memory cell structure having at least one second active region of at least one second memory cell, wherein the second memory cell structure is disposed above the first memory cell structure; and

forming a memory cell contact structure configured to electrically couple the first memory cell structure and the second memory cell structure, such that the memory cell contact structure has a staircase structure, a first step of which is configured to electrically contact the first memory cell structure, and a second step of which is configured to electrically contact the second memory cell structure, wherein the first step and the second step each comprises a first doped region doped with doping atoms of a first conductivity type, wherein the memory cell contact structure further comprises second doped regions doped with doping atoms of a second conductivity type, wherein the second conductivity type is different from the first conductivity type, wherein the second doped regions are disposed next to the first doped regions in the first direction.