Chip structure and process for forming the same

• US 7,915,734 B2
• Filed: 02/18/2008
• Issued: 03/29/2011
• Est. Priority Date: 12/13/2001
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan, Huang, Ching-Cheng
• Primary Examiner(s): Zarneke; David A
• Application Number:
  US12/032,706
• Publication Number:
  US 20080142979A1
• Time in Patent Office: 1,135 Days
• Field of Search: 257/759, 257/758, 257/750, 257/763, 257/762, 257/E23.011, 257/E23.012, 257/E23.02
• US Class Current: 257/759
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05073 Single internal layer
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0558 being stacked
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05657 Cobalt [Co] as principal constituent
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 27/0248 : for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.

Claims

1. A chip comprising:

a silicon substrate;

a transistor in or on said silicon substrate;

a first copper layer over said silicon substrate;

a second copper layer over said first copper layer and said silicon substrate;

a dielectric layer between said first and second copper layers;

a copper plug in said dielectric layer and between said first and second copper layers, wherein said copper plug connects said first and second copper layers;

a first conductive pad over said silicon substrate;

a second conductive pad over said silicon substrate;

a passivation layer over said first and second copper layers and said dielectric layer, wherein said passivation layer comprises a nitride layer, wherein a first opening in said passivation layer is over a first contact point of said first conductive pad, and said first contact point is at a bottom of said opening, and wherein a second opening in said passivation layer is over a second contact point said second conductive pad, and said second contact point is at a bottom of said opening, wherein said first opening has a width between 0.5 and 20 micrometers;

a first polymer layer on said passivation layer, wherein a third opening in said first polymer layer is over said first contact point, and a fourth opening in said first polymer layer is over said second contact point, and wherein said first polymer layer has a thickness between 1 and 100 micrometers; and

an interconnecting structure on a top surface of said first polymer layer and on said first and second contact points, wherein said first contact point is connected to said second contact point through said interconnecting structure, wherein said interconnecting structure comprises a conductive layer on top surface of said first polymer layer and an electroplated copper layer on said conductive layer.

2. The chip of claim 1, wherein said first polymer layer comprises polyimide.

3. The chip of claim 1, wherein said first polymer layer comprises benzocyclobutene (BCB).

4. The chip of claim 1 further comprising a second polymer layer on said interconnecting structure and said first polymer layer.

5. The chip of claim 4, wherein said second polymer layer comprises polyimide.

6. The chip of claim 1, wherein said interconnecting structure has a thickness between 1 and 50 micrometers.

7. The chip of claim 1, wherein said conductive layer comprises titanium.

8. The chip of claim 1, wherein said conductive layer comprises a titanium-tungsten alloy.

9. The chip of claim 1, wherein said conductive layer comprises chromium.

10. The chip of claim 1, wherein said interconnecting structure comprises a ground interconnecting said first contact point to said second contact point.

11. A chip comprising:

a silicon substrate;

a transistor in or on said silicon substrate;

a first copper layer over said silicon substrate;

a second copper layer over said first copper layer and said silicon substrate;

a dielectric layer between said first and second copper layers;

a copper plug in said dielectric layer and between said first and second copper layers, wherein said copper plug connects said first and second copper layers;

a first conductive pad over said silicon substrate;

a second conductive pad over said silicon substrate;

a passivation layer over said first and second copper layers and said dielectric layer, wherein said passivation layer comprises a nitride, wherein a first opening in said passivation layer is over a first contact point of said first conductive pad, and said first contact point is a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of said second conductive pad, and said second contact point is at a bottom of said second opening, wherein said first opening has a width between 0.5 and 20 micrometers;

a first polymer layer on said passivation layer, wherein a third opening in said first polymer layer is over said first contact point, and a fourth opening in said first polymer layer is over said second contact point, and wherein said first polymer layer has a thickness between 1 and 100 micrometers;

an interconnecting structure on a top surface of said first polymer layer and on said first and second contact points, wherein said first contact point is connected to said second contact point through said interconnecting structure, wherein said interconnecting structure comprises a conductive layer on said top surface of said first polymer layer and an electroplated copper layer on said conductive layer; and

a second polymer layer on said interconnecting structure and on said first polymer layer.

12. The chip of claim 11, wherein said first polymer layer comprises polyimide.

13. The chip of claim 11, wherein said first polymer layer comprises benzocyclobutene (BCB).

14. The chip of claim 11, wherein said interconnecting structure comprises a power interconnect connecting said first contact point to said second contact point.

15. The chip of claim 14, wherein said second polymer layer comprises polyimide.

16. The chip of claim 11, wherein said interconnecting structure has a thickness between 1 and 50 micrometers.

17. The chip of claim 11, wherein said interconnecting layer comprises titanium.

18. The chip of claim 11, wherein said interconnecting layer comprises a titanium-tungsten alloy.

19. The chip of claim 11, wherein said interconnecting layer comprises chromium.

20. The chip of claim 11, wherein said interconnecting structure comprises a ground interconnecting said first contact point to said second contact point.

21. A chip comprising:

a silicon substrate;

a transistor in or on said silicon substrate;

a first copper layer over said silicon substrate;

a second copper layer over said first copper layer and said silicon substrate;

a dielectric layer between said first and second copper layers;

a copper plug in said dielectric layer and between said first and second copper layers, wherein said copper plug connects said first and second copper layers;

a first conductive pad over said silicon substrate;

a second conductive pad over said silicon substrate;

a passivation layer over said silicon substrate, said first and second copper layers and said dielectric layer, wherein a first opening in said passivation layer is over a first contact point of said first conductive pad, and said first contact point is at a bottom of said first opening, wherein said first opening has a width between 0.5 and 20 micrometers, and wherein a second opening in said passivation layer is over a second contact point of said second conductive pad, and said second contact point is at a bottom of said second opening, wherein said passivation layer comprises a nitride;

a first metal interconnect on said first and second contact points and over said passivation layer, wherein said first contact point is connected to said second contact point through said first metal interconnect, wherein said first metal interconnect comprises a first conductive layer and a third copper layer on said first conductive layer, wherein said first metal interconnect has a thickness between 1 and 50 micrometers;

a polymer layer over said first metal interconnect and said passivation layer, wherein a third opening in said polymer layer is over a third contact point of said first metal interconnect, wherein said third opening is vertically over said first contact point, wherein said polymer layer has a thickness between 1 and 100 micrometers; and

a second metal interconnect on said third contact point, on said polymer layer and vertically over said first and second contact points, wherein said second metal interconnect comprises a second conductive layer and a fourth copper layer on said second conductive layer.

22. The chip of claim 21, wherein said first conductive layer comprises titanium.

23. The chip of claim 21, wherein said second conductive layer comprises titanium.

24. The chip of claim 21, wherein said polymer layer comprises polyimide.

25. A chip comprising:

a silicon substrate;

a transistor in or on said silicon substrate;

a first copper layer over said silicon substrate;

a second copper layer over said first copper layer and said silicon substrate;

a dielectric layer between said first and second copper layers;

a copper plug in said dielectric layer and between said first and second copper layers, wherein said copper plug connects said first and second copper layers;

a first conductive pad over said silicon substrate;

a second conductive pad over said silicon substrate;

a layer of an inorganic compound over said silicon substrate, said first and second copper layers and said dielectric layer, wherein a first opening in said layer of said inorganic compound is over a first contact point of said first conductive pad, and said first contact point is at a bottom of said first opening, wherein said first opening has a width between 0.5 and 20 micrometers, and wherein a second opening in said layer of said inorganic compound is over a second contact point of said second conductive pad, and said second contact point is at a bottom of said second opening;

a first metal interconnect on said first and second contact points and over said layer of said inorganic compound, wherein said first contact point is connected to said second contact point through said first metal interconnect, wherein said first metal interconnect comprises a first conductive layer and a third copper layer on said first conductive layer, wherein said first metal interconnect has a thickness between 1 and 50 micrometers;

a polymer layer over said first metal interconnect and over said layer of said inorganic compound, wherein said polymer layer covers a top surface and sidewall of said first metal interconnect, wherein a third opening in said polymer layer is over a third contact point of said first metal interconnect, wherein said third opening is vertically over said first contact point, wherein said polymer layer has a thickness between 1 and 100 micrometers; and

a second metal interconnect on said third contact point, on said polymer layer and vertically over said first and second contact points, wherein said second metal interconnect comprises a second conductive layer and a fourth copper layer on said second conductive layer.

26. The chip of claim 25, wherein said first conductive layer comprises titanium.

27. The chip of claim 25, wherein said second conductive layer comprises titanium.

28. The chip of claim 25, wherein said polymer layer comprises polyimide.