Electroluminescent display device with scrolling addressing

• US 7,916,099 B2
• Filed: 10/05/2004
• Issued: 03/29/2011
• Est. Priority Date: 10/09/2003
• Status: Active Grant

• Current Assignee: Beijing Xiaomi Mobile Software Co., Ltd. (Xiaomi Corp.)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Budzelaar, Franciscus P. M., Steer, William A., Fish, David A.
• Primary Examiner(s): Wang; Quan-Zhen
• Assistant Examiner(s): Chow; Yuk
• Application Number:
  US10/574,445
• Publication Number:
  US 20070262928A1
• Time in Patent Office: 2,366 Days
• Field of Search: 345/76, 345/77, 345/205, 345/210, 345/211, 702/189, 257/59
• US Class Current: 345/76
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0852 being a dynamic memory with more than one capacitor
• CPC Class Codes: G09G 2300/0861 with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2320/0261 in the context of movement of objects on the screen or movement of the observer relative to the screen
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 2320/0606 Manual adjustment
• CPC Class Codes: G09G 2320/0626 for control of overall brightness
• CPC Class Codes: G09G 3/2011 by amplitude modulation
• CPC Class Codes: G09G 3/2014 by modulation of the duration of a single pulse during which the logic level remains constant
• CPC Class Codes: G09G 3/2081 with combination of amplitude modulation and time modulation space and time error diffusion G09G3/2066
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes

Abstract

An active matrix electroluminescent display has means for interrupting the drive of current through the display element. Row driver circuitry for the display has a shift register and logic arrangement (50, 54) for generating the drive voltage for the interrupting means, and which includes a pulse having a duration which can be varied up to substantially the full field period less the address period. The signal or signals propagated through the shift register arrangement (50) control the pulse duration. This arrangement provides reduced driver complexity to allow control for the row by row addressing of the pixels with control of the overall light emission period of each row. The control enables a scrolling addressing scheme to be implemented.

Claims

1. An active matrix electroluminescent display device comprising an array of display pixels arranged in rows and columns, each pixel comprising:

an electroluminescent (EL) display element;

a drive transistor for driving a current through the display element;

means for directly interrupting the drive of current through the display element via a direct interrupt signal, said direct interruption means being provided in series with the electroluminescent display element; and

row driver circuitry for generating control voltages to be applied to the pixels in each row in sequence including a drive voltage as input to the interrupting means,

wherein the row driver circuitry comprises a shift register arrangement and logic arrangement for generating the drive voltage for the interrupting means, the drive voltage for the interrupting means including a long emission time pulse for controlling the output of the display element, the long emission time pulse having a duration which can be varied up to substantially the full field period less the address period, and wherein the timing of the end of the long emission time pulse corresponds to the timing of the direct interrupt signal generated by the interrupting means for controlling the display element illumination time,

wherein the signal or signals propagated through the shift register arrangement control the pulse duration.

2. A device as claimed in claim 1, wherein the shift register arrangement and logic arrangement comprises first and second shift register devices, each having a pulse propagating through them, and logic means for deriving a signal having a pulse with duration derived from the difference in timing of the pulses propagating through the first and second shift register devices.

3. A device as claimed in claim 1, wherein the pulse propagating in each shift register device has a duration corresponding the line time of the display.

4. A device as claimed in claim 1, wherein the logic means comprises a transmission gate which transmits a low pulse in response to a pulse on one of the shift register devices and transmits a high pulse in response to a pulse on the other one of the shift register devices.

5. A device as claimed in claim 4, wherein the logic means further comprises a memory cell for maintaining a constant output between pulses received from the transmission gate.

6. A device as claimed in claim 1, wherein the shift register arrangement and logic arrangement comprises first and second shift register devices, each having a pulse propagating through them, and logic means for deriving a signal having a pulse with duration derived from the duration of the pulse in one of the first and second shift register devices.

7. A device as claimed in claim 6, wherein the pulse propagating in one shift register device has a duration corresponding to the line time of the display and the pulse propagating in the other shift register device has a duration for controlling the display element illumination period.

8. A device as claimed in claim 1, wherein the shift register arrangement and logic arrangement comprises a shift register device, having a pulse propagating through it having a duration dependent on the desired illumination time of the display element, and logic means for deriving from the shift register device a pulse having a duration corresponding to the line time of the display.

9. A device as claimed in claim 8, wherein the logic means for deriving from the shift register device a pulse having a duration corresponding to the line time of the display comprises a combination element for combining the pulse at the output of one shift register element (n) for one row with the pulse at the output of another shift register element (n+1) for an adjacent row.

10. A device as claimed in claim 1, wherein each pixel comprises drive transistor threshold compensation circuitry.

11. A device as claimed in claim 10, wherein the drive transistor, the electroluminescent display element and means for interrupting the drive of current through the display element are connected in series between a power supply line and a common potential line.

12. A device as claimed in claim 11, wherein the means for interrupting comprises a transistor.

13. An active matrix electroluminescent display device comprising an array of display pixels arranged in rows and columns, each pixel comprising:

an electroluminescent (EL) display element;

a drive transistor for driving a current through the display element;

means for interrupting the drive of current through the display element; and

row driver circuitry for generating control voltages to be applied to the pixels in each row in sequence including a drive voltage for the interrupting means,

wherein the row driver circuitry comprises a shift register arrangement and logic arrangement for generating the drive voltage for the interrupting means, the drive voltage for the interrupting means including a pulse having a duration which can be varied up to substantially the full field period less the address period,

wherein the signal or signals propagated through the shift register arrangement controls the pulse duration,

wherein a first pulse from the shift register arrangement and logic arrangement is combined with a first template control signal or signals (A1, A2) to provide a first control signal or signals (A1r,A2r) for the addressing of the pixel, and a second pulse from the shift register arrangement and logic arrangement is combined with a second template control signal (A3) to provide the drive voltage (A3r) for the interrupting means both during the addressing of the pixel and during subsequent driving of the pixel.

14. A device as claimed in claim 13, wherein the first pulse has duration equal to the line time.

15. A device as claimed in claim 13, wherein the second pulse has duration selected to control the display element illumination time.

16. An active matrix electroluminescent display device comprising an array of display pixels arranged in rows and columns, each pixel comprising:

an electroluminescent (EL) display element;

a drive transistor for driving a current through the display element;

means for interrupting the drive of current through the display element; and

row driver circuitry for generating control voltages to be applied to the pixels in each row in sequence including a drive voltage for the interrupting means,

wherein the row driver circuitry comprises a shift register arrangement and logic arrangement for generating the drive voltage for the interrupting means, the drive voltage for the interrupting means including a pulse having a duration which can be varied up to substantially the full field period less the address period,

wherein the signal or signals propagated through the shift register arrangement controls the pulse duration,

wherein each pixel comprises drive transistor threshold compensation circuitry,

wherein the drive transistor threshold compensation circuitry comprises first and second capacitors connected in series between the gate and source of the drive transistor, a data input to the pixel being provided to the junction between the first and second capacitors thereby to charge the first capacitor to a voltage derived from the pixel data voltage, and a voltage derived from the drive transistor threshold voltage being stored on the second capacitor.

17. A method of driving an active matrix electroluminescent display device comprising an array of display pixels arranged in rows and columns, in which each pixel comprises an electroluminescent (EL) display element, a drive transistor for driving a current through the display element and means for directly interrupting the drive of current through the display element provided in series with the electroluminescent display element, the method comprising:

propagating a pulse or pulses through a shift register arrangement;

using a pulse from the shift register arrangement to allow pixel addressing control voltages to be applied to the pixels of a row during an addressing period;

using the shift register pulse or pulses to derive a drive voltage as input to the interrupting means including a long emission time pulse for controlling the output of the display element, the long emission time pulse having a duration which can be varied up to substantially the full field period less the addressing period; and

applying the drive voltage for the interrupting means to the interrupting means after the pixel addressing period, the timing of the end of the pulse corresponding to the timing of an interrupt by the means for interrupting,

wherein the shift register arrangement and logic arrangement comprises first and second shift register devices, each having a pulse propagating through them, and logic means for deriving a signal having a long emission time pulse derived from the difference in timing of the pulses propagating through the first and second shift register devices, and

wherein said derived signal is synchronized to the frame time.