Non-volatile memory read/write verify

• US 7,916,515 B2
• Filed: 03/10/2009
• Issued: 03/29/2011
• Est. Priority Date: 03/10/2009
• Status: Expired due to Fees

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Li, Hai, Liu, Harry Hongyue, Wang, Alan Xuguang, Chen, Yiran
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US12/401,438
• Publication Number:
  US 20100232206A1
• Time in Patent Office: 749 Days
• Field of Search: 365/148, 365/173
• US Class Current: 365/148
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1677 Verifying circuits or methods
• CPC Class Codes: G11C 11/1693 Timing circuits or methods
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0066 Verify correct writing whilst writing is in progress, e.g. by detecting onset or cessation of current flow in cell and using the detector output to terminate writing

Abstract

An apparatus and associated method for writing data to a non-volatile memory cell, such as a resistive random access memory (RRAM) cell. In some embodiments, a control circuitry is configured to write a logic state to a resistive sense element while simultaneously verifying the logic state of the resistive sense element.

Claims

1. An apparatus comprising control circuitry configured to write a logic state to a resistive sense element (RSE) while simultaneously verifying the written logic state of the RSE, a first sense amplifier coupled to the RSE which is used during said simultaneous verification, and a second sense amplifier coupled to the RSE which is used to read the written logic state of the RSE during a subsequent read operation.

2. The apparatus of claim 1, wherein the logic state of the RSE is written by an application of a write current to the RSE, and wherein the written logic state is simultaneously verified by sensing a voltage drop across the RSE during the application of the write current.

3. The apparatus of claim 1, wherein the RSE is marked as defective after an error is detected during said simultaneous verification.

4. The apparatus of claim 1, wherein a first reference voltage is supplied to the first sense amplifier and a different, second reference voltage is supplied to the second sense amplifier.

5. The apparatus of claim 1, wherein the first sense amplifier receives as an input a voltage drop across the RSE, said voltage drop generated during passage of a write current through the RSE to write the logical state.

6. The apparatus of claim 5, wherein the first sense amplifier compares the voltage drop to a first reference voltage responsive to a first value for the written logical state, and wherein the first sense amplifier compares the voltage drop to a second reference voltage responsive to a second value for the written logical state.

7. The apparatus of claim 1, wherein the writing of the RSE and verification of the logic state uses a single write current pulse.

8. The apparatus of claim 1, wherein the writing of the RSE and verification of the logic state occurs over a single write clock cycle.

9. The apparatus of claim 1, wherein the RSE is characterized as a magnetic tunneling junction (MTJ).

10. A method comprising:

writing a logical state to a resistive sense element (RSE) by applying a write current to the RSE to write the logical state thereto, the applied write current generating a voltage drop across the RSE; and

simultaneously verifying the written logical state of the RSE during the writing step by sensing said voltage drop.

11. The method of claim 10, wherein the RSE is marked as defective after an error is detected.

12. The method of claim 10, wherein the RSE is connected to a plurality of sense amplifiers.

13. The method of claim 12, wherein a multiplexer provides reference values to each sense amplifier.

14. The method of claim 13, wherein the reference values are respectively used for a write operation and a read operation.

15. The method of claim 10, wherein the simultaneously verifying step comprises using a sense amplifier to compare the voltage drop to a reference voltage.

16. A memory, comprising:

an array of memory cells each comprising a resistive sense element (RSE);

a write circuit adapted to apply a write current to a selected memory cell of the array to write a logical state to the associated RSE of said cell, the write current generating a voltage drop across the cell; and

a sense amplifier adapted to simultaneously verify the written logic state by comparing the voltage drop to a reference voltage.

17. The memory of claim 16, in which the sense amplifier outputs a data signal in response to the voltage drop and the reference voltage, the data signal having a value indicative of the written logic state of the RSE.

18. The memory of claim 17, in which the reference voltage has a magnitude selected in relation to the written logic state so that a first reference voltage is used for a first written logic state and a different, second reference voltage is used for a different, second written logic state.

19. The memory of claim 18, further comprising a multiplexor circuit which respectively presents the first and second reference voltages to the sense amplifier responsive to an input signal indicative of said logic state.

20. The memory of claim 16, in which the sense amplifier is characterized as a first sense amplifier, the storage device further comprising a second sense amplifier coupled to the RSE which is used to subsequently verify the written logic state of the RSE responsive to an application of a read current through the selected memory cell during a subsequent read operation.