Memory device employing NVRAM and flash memory cells

• US 7,916,538 B2
• Filed: 12/18/2008
• Issued: 03/29/2011
• Est. Priority Date: 01/28/2008
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jeon, Byung-gil, Jeong, Hong-sik, Min, Byung-jun
• Primary Examiner(s): Ho; Hoai V
• Assistant Examiner(s): Hidalgo; Fernando N
• Application Number:
  US12/337,950
• Publication Number:
  US 20090190401A1
• Time in Patent Office: 831 Days
• Field of Search: 365/185.05, 365/189.05, 365/230.06, 365/185.18, 365/185.11, 365/185.12, 365/185.23, 365/132, 365/189.2
• US Class Current: 365/185.05
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series

Abstract

A memory device includes a memory cell array including a NAND flash cell portion including a plurality of first columns of serially-connected flash memory cells and a non-volatile random access memory (NVRAM) cell portion including a plurality of second columns of NVRAM cells. The flash memory cells and the NVRAM cells are arranged such that respective word lines are connected to flash memory cells and NVRAM cells in each of respective rows, which may correspond to page units including flash memory cells and NVRAM cells.

Claims

1. A memory device comprising:

a memory cell array comprising a NAND flash cell portion comprising a plurality of first columns of serially connected flash memory cells and an NVRAM cell portion comprising a plurality of second columns of NVRAM cells,

wherein the flash memory cells and the NVRAM cells are arranged such that respective word lines are connected to flash memory cells and NVRAM cells in each of respective rows and wherein the respective rows correspond to respective page units including flash memory cells and NVRAM cells.

2. The memory device of claim 1, wherein a spare area and/or a data area of the memory cell array comprises NVRAM cells.

3. The memory device of claim 1, wherein the NVRAM cells comprise FRAM cells, MRAM cells or PRAM cells.

4. A memory device comprising:

a memory cell array comprising a NAND flash cell portion comprising a plurality of first columns of serially connected flash memory cells and an NVRAM cell portion comprising a plurality of second columns of NVRAM cells, wherein the flash memory cells and the NVRAM cells are arranged such that respective word lines are connected to flash memory cells and NVRAM cells in each of respective rows;

a first sense amplifier and page buffer circuit configured to receive data from the NVRAM cell portion;

a second sense amplifier and page buffer circuit configured to receive data from the NAND flash cell portion;

a first column gating circuit coupled to the first sense amplifier and page buffer circuit;

a second column gating circuit coupled to the second sense amplifier and page buffer circuit;

a data input/output buffer circuit coupled to the first column gating circuit and the second column gating circuit; and

control circuitry coupled to the NVRAM cell portion, the NAND flash cell portion, the first and second sense amplifier and page buffer circuits, the first and second column gating circuits and the data/input output buffer circuit and configured to support transfer of data from a NVRAM cell portion of a row through the first sense amplifier and page buffer circuit, the first column gating circuit and the data input/output buffer circuit concurrent with sensing and storing of data from a NAND flash cell portion of the row by the second sense amplifier and page buffer circuit.

5. The memory device of claim 4, wherein the control circuitry is configured to support output of data from the NVRAM cell portion of the row via the data input/output buffer circuit simultaneous with transfer of data from the NAND flash cell portion of the row to the second sense amplifier and page buffer circuit.

6. A memory device comprising:

a memory cell array comprising a NAND flash cell portion and an NVRAM cell portion arranged such that respective word lines are connected to flash memory cells and NVRAM cells in each of respective rows;

a row decoder circuit configured to selectively activate the word lines;

a first sense amplifier and page buffer circuit configured to sense and amplify data on bitlines of the NVRAM cell portion and to store the sensed and amplified data;

a second sense amplifier and page buffer circuit configured to sense and amplify data on bitlines in the NAND flash cell portion and to store the sensed and amplified data;

a data input/output buffer circuit configured to transmit data on an external input/output pin;

a first column gating circuit coupled between the first sense amplifier and page buffer circuit and the data input/output buffer circuit;

a second column gating circuit coupled between the second sense amplifier and page buffer circuit and the data input/output buffer circuit;

a first column decoder circuit configured to decode first column addresses and to responsively cause the first column gating circuit to selectively provide stored data from the first sense amplifier and page buffer circuit to the data input/output buffer circuit; and

a second column decoder circuit configured to decode second column addresses and to responsively cause the second column gating circuit to selectively provide stored data from the second sense amplifier and page buffer circuit to the data input/output buffer circuit.

7. The memory device of claim 6, wherein a spare portion and/or a data portion of the memory cell array comprises NVRAM cells.

8. The memory device of claim 6, wherein the NVRAM cell portion comprises FRAM cells, MRAM cells, or PRAM cells.

9. The memory device of claim 6, further comprising control circuitry coupled to the row decoder circuit, the first column decoder circuit, the second column decoder circuit and the data input/output buffer circuit and configured to support transfer of data from a NVRAM cell portion of a row through the first sense amplifier and page buffer circuit, the first column gating circuit and the data input/output buffer circuit concurrent with sensing and storing data from a NAND flash cell portion of the row by the second sense amplifier and page buffer circuit.

10. The memory device of claim 9, wherein the control circuitry is configured to support output of data from the NVRAM cell portion of the row via the data input/output circuit simultaneous with transfer of data from the NAND flash cell portion of the row to the second sense amplifier and page buffer circuit.

11. The memory device of claim 6, further comprising a write buffer circuit configured to store erase information and page information for the NAND flash cell portion.

12. The memory device of claim 11, wherein the write buffer circuit comprises NVRAM cells.

13. The memory device of claim 11, wherein the write buffer circuit has a capacity to store sufficient write data to fill a block of the memory cell array after an erasing operation on the NAND flash cell area.

14. The memory device of claim 11, further comprising a write buffer circuit controller configured to select a block and page to write the write data via the erase information and the page information of the write buffer circuit.

15. The memory device of claim 14, wherein the write buffer circuit controller is configured to write data in a NVRAM cell portion of a selected page before writing data to a NAND flash cell portion of the selected page.