Systems and methods for saving power in a digital broadcast receiver

• US 7,916,711 B2
• Filed: 05/03/2007
• Issued: 03/29/2011
• Est. Priority Date: 03/24/2005
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: SiPort, Inc. (Intel Corporation)
• Inventors: Waxman, Shay, Arad, Oren
• Primary Examiner(s): LEE, CHI HO A
• Application Number:
  US11/800,209
• Publication Number:
  US 20070218936A1
• Time in Patent Office: 1,426 Days
• Field of Search: None
• US Class Current: 370/347
• CPC Class Codes: H04H 20/42 Arrangements for resource management
• CPC Class Codes: H04H 20/426 Receiver side
• CPC Class Codes: H04H 20/72 of terrestrial networks
• CPC Class Codes: H04H 2201/20 digital audio broadcasting [DAB]
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

Systems and methods for conserving power in a receiver device are provided. In exemplary embodiments, a receiver device comprises a tuner configured to receive a transmitted signal, at least one analog-to-digital converter (ADC), and a digital signal processing hardware comprising a control logic. The exemplary control logic is configured to determine if a symbol within the transmitted signal belongs to an erasure interval, and generate a control signal to configure a receiver device component to conserve power based on the determination.

Claims

1. A system for power conservation in a receiver device, comprising:

a tuner configured to receive a transmitted signal of modulated information intended for the receiver device, wherein the modulated information includes symbols;

an analog-to-digital converter (ADC) that samples the received transmitted signal provided by the tuner; and

digital signal processing hardware (DSPHW) that;

extracts soft bit information from the sampled signal provided by at least one analog-to-digital converter,

determines if a symbol included in the sampled signal belongs to an erasure interval, wherein the erasure interval covers a set of symbols for which the soft bit information is replaced with information that is not provided by an analog-to-digital converter,

generates a control signal to configure a receiver device component to conserve power based on the determination, and

recovers the modulated information based on the extracted soft bit information in spite of an occurrence of an erasure interval.

2. The system of claim 1 wherein the DSPHW further performs clock gating to conserve power in the receiver device.

3. The system of claim 1 wherein the tuner component transitions between different power modes responsive to the control signal.

4. The system of claim 1 wherein the DSPHW further generates a wakeup signal to activate a receiver device component.

5. The system of claim 1, wherein the DSPHW further updates a duration of the erasure interval based on an estimated signal-to-noise ratio of the sampled signal and a reception coding margin of the sampled signal, wherein the reception coding margin is based on a difference between a maximum allowed bit error rate threshold and a decoded bit error rate.

6. The system of claim 1, wherein the DSPHW further streams erased bits based on the determination.

7. A method for power conservation in a receiver device, comprising:

receiving a transmitted signal of modulated information intended for the receiver device, wherein the modulated information includes symbols;

extracting soft bit information from the transmitted signal;

determining if a symbol within the transmitted signal belongs to an erasure interval, wherein the erasure interval covers a set of symbols for which the soft bit information is replaced with other information;

generating a control signal to configure a receiver device component to conserve power based on the determination; and

recovering the modulated information based on the extracted soft bit information in spite of an occurrence of an erasure interval.

8. The method of claim 7 wherein generating the control signal further conserves the power of a tuner component.

9. The method of claim 7 wherein the generated control signal further conserves the power of a DSPHW component.

10. The method of claim 7 wherein the generated control signal further conserves the power of the ADC.

11. The method of claim 7 further comprising clock gating, wherein the clock gating conserves power of the receiver device.

12. The method of claim 7 wherein the generated control signal transitions a tuner component between different power modes.

13. The method of claim 7 further comprising generating a wakeup signal that activates a receiver device component.

14. The method of claim 7, further comprising updating a duration of the erasure interval based on an estimated signal-to-noise ratio of the transmitted signal and a reception coding margin of the transmitted signal, wherein the reception coding margin is based on a difference between a maximum allowed bit error rate threshold and a decoded bit error rate.

15. The method of claim 7 further comprising streaming erased bits based on the determination.

16. A system for power conservation in a receiver device, comprising:

means for receiving a transmitted signal of modulated information intended for the receiver device, wherein the modulated information includes symbols;

means for extracting soft bit information from the transmitted signal;

means for determining if a symbol within the transmitted signal belongs to an erasure interval, wherein the erasure interval covers a set of symbols for which the soft bit information is replaced with other information;

means for generating a control signal to configure a receiver device component to conserve power based on the determination;

means for recovering the modulated information based on the extracted soft bit information in spite of an occurrence of an erasure interval.

17. The system of claim 16 further comprising a means for streaming erased bits based on the determination.