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Systems and methods for testing and diagnosing delay faults and for parametric testing in digital circuits

  • US 7,917,319 B2
  • Filed: 02/06/2008
  • Issued: 03/29/2011
  • Est. Priority Date: 02/06/2008
  • Status: Active Grant
First Claim
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1. A method of performing delay-fault testing on an integrated circuit, comprising:

  • providing an integrated circuit comprising combinational logic that includes a plurality of data paths outputting corresponding respective data bits to a plurality of memory elements;

    clocking the combinational logic and ones of the plurality of memory elements with a first clock signal having a period;

    simultaneously with said clocking with the first clock signal, providing a particular memory element of the plurality of memory elements with a shorter launch-capture cycle that is shorter than the period of the first clock signal, the shorter launch-capture cycle being implemented using two separate, but simultaneous, delayed clocks; and

    determining whether a delay fault occurred on the particular data path of the plurality of data paths corresponding to the particular memory element provided with the shorter launch-capture cycle as a function of the shorter launch-capture cycle.

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