Systems and methods for testing and diagnosing delay faults and for parametric testing in digital circuits

• US 7,917,319 B2
• Filed: 02/06/2008
• Issued: 03/29/2011
• Est. Priority Date: 02/06/2008
• Status: Active Grant

• Current Assignee: DFT Microsystems, Inc.
• Original Assignee: DFT Microsystems, Inc.
• Inventors: Hafed, Mohamed M.
• Primary Examiner(s): Wachsman; Hal D
• Application Number:
  US12/026,760
• Publication Number:
  US 20090198461A1
• Time in Patent Office: 1,147 Days
• Field of Search: 702/69, 702/79, 702/80, 702/117, 702/118, 702/125
• US Class Current: 702/69
• CPC Class Codes: G01R 31/31858 Delay testing

Abstract

Delay-fault testing and parametric analysis systems and methods utilizing one or more variable delay time-base generators. In embodiments of the delay-fault testing systems, short-delay logic paths are provided with additional scan-chain memory elements and logic that, in conjunction with the one or more variable-delay time-base generators, provides the effect of over-clocking without the need to over-clock. Related methods provide such effective over-clocking. In embodiments of parametric analysis systems, test point sampling elements and analysis circuitry are clocked as a function of the output of the one or more variable-delay time-base generators to provide various parametric analysis functionality. Related methods address this functionality.

Claims

1. A method of performing delay-fault testing on an integrated circuit, comprising:

providing an integrated circuit comprising combinational logic that includes a plurality of data paths outputting corresponding respective data bits to a plurality of memory elements;

clocking the combinational logic and ones of the plurality of memory elements with a first clock signal having a period;

simultaneously with said clocking with the first clock signal, providing a particular memory element of the plurality of memory elements with a shorter launch-capture cycle that is shorter than the period of the first clock signal, the shorter launch-capture cycle being implemented using two separate, but simultaneous, delayed clocks; and

determining whether a delay fault occurred on the particular data path of the plurality of data paths corresponding to the particular memory element provided with the shorter launch-capture cycle as a function of the shorter launch-capture cycle.

2. A method according to claim 1, wherein the plurality of data paths have differing delays and the method further comprises selecting the particular data path due to the particular data path having a short delay relative to the differing delays.

3. A method according to claim 1, wherein the combinational logic has a mission-mode speed and said clocking with said first clock signal includes clocking at the mission-mode speed.

4. A method according to claim 1, wherein said providing with a shorter launch-capture cycle includes clocking the particular memory element with a second clock signal that is delayed by a predetermined amount.

5. A method according to claim 4, further comprising generating the second clock signal by continually selecting between differing delayed versions of a reference clock to provide a combined signal and, then, phase-filtering the combined signal.

6. A method according to claim 1, wherein said determining of whether a delay fault occurred includes performing a logical operation on an output of the particular memory element and an output of an additional memory element operatively connected to the particular data path in parallel with the particular memory element.

7. A method according to claim 6, wherein said performing of the logical operation includes XORing together the output of the particular memory element and the output of an additional memory element.

8. A method according to claim 6, wherein said performing of the logical operation produces a logic result and said determining of whether a delay fault occurred includes capturing the logic result using a memory element clocked with the first clock signal.

9. A method of implementing delay-fault testing for an integrated circuit, comprising:

during a design phase of designing an integrated circuit, identifying small delay paths from a plurality of data paths;

providing ones of the plurality of data paths with a corresponding respective plurality of first scannable memory elements;

providing the integrated circuit with additional, second scannable memory elements to the outputs of the small delay paths;

providing the integrated circuit with further, third scannable memory elements in communication with corresponding respective ones of the second scannable memory elements, the third scannable memory elements for capturing delay-fault signals;

providing the integrated circuit with a functional clock network for providing a first clock signal to the plurality of data paths and the plurality of first scannable memory elements;

providing the integrated circuit with a time-base generator for providing a second clock signal to the second scannable memory elements, the second clock signal having a delay relative to the first clock signal;

programming the time-base generator so that the delay is an optimal value;

scanning appropriate data values for transition fault testing into the plurality of first scannable memory elements and the second scannable memory elements;

performing the transition fault testing using the first and second clock signals simultaneously with one another; and

subsequent to said performing of the transition fault testing, scanning test values out of at least the third scannable memory elements.

10. A method according to claim 9, further comprising programming the time-base generator with differing values and determining ones of the differing values that correctly pass known-good devices and that correctly measure small delay paths.