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Method of switching external models in an automated system-on-chip integrated circuit design verification system

  • US 7,917,348 B2
  • Filed: 01/07/2008
  • Issued: 03/29/2011
  • Est. Priority Date: 02/01/2002
  • Status: Active Grant
First Claim
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1. A method for verifying an integrated circuit design comprising:

  • providing a simulation model of an I/O controller connected to one or more simulated I/O cores, said simulated I/O cores part of said integrated circuit design;

    providing a simulation model of an external memory mapped test device having a simulated switch for selectively connecting one or more of said simulated I/O cores to corresponding simulated one or more I/O driver models;

    providing a simulated bus for transferring signals between said I/O controller and said switch;

    storing a test case comprising computer-executable instructions on an external memory device;

    providing a test operating system for controlling said switch;

    simulating said integrated circuit design by running said test case on said test operating system; and

    wherein said external memory mapped test device is a software module, said simulated I/O cores and said simulated I/O controller are software descriptions of said integrated circuit design and said external memory mapped test device, said simulated I/O cores and said simulated I/O controller and said test case are executable by said test operating system on an embedded processor to perform verification of said integrated circuit design.

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