Method of switching external models in an automated system-on-chip integrated circuit design verification system
First Claim
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1. A method for verifying an integrated circuit design comprising:
- providing a simulation model of an I/O controller connected to one or more simulated I/O cores, said simulated I/O cores part of said integrated circuit design;
providing a simulation model of an external memory mapped test device having a simulated switch for selectively connecting one or more of said simulated I/O cores to corresponding simulated one or more I/O driver models;
providing a simulated bus for transferring signals between said I/O controller and said switch;
storing a test case comprising computer-executable instructions on an external memory device;
providing a test operating system for controlling said switch;
simulating said integrated circuit design by running said test case on said test operating system; and
wherein said external memory mapped test device is a software module, said simulated I/O cores and said simulated I/O controller are software descriptions of said integrated circuit design and said external memory mapped test device, said simulated I/O cores and said simulated I/O controller and said test case are executable by said test operating system on an embedded processor to perform verification of said integrated circuit design.
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Abstract
A system and method for verifying an integrated circuit design is provided. The system comprising: an I/O controller connected to one or more I/O cores, the I/O cores part of the integrated circuit design; an external memory mapped test device having a switch for selectively connecting one or more of the I/O cores to corresponding I/O driver models; a bus for transferring signals between the I/O controller and the switch; and a test operating system for controlling the switch.
6 Citations
13 Claims
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1. A method for verifying an integrated circuit design comprising:
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providing a simulation model of an I/O controller connected to one or more simulated I/O cores, said simulated I/O cores part of said integrated circuit design; providing a simulation model of an external memory mapped test device having a simulated switch for selectively connecting one or more of said simulated I/O cores to corresponding simulated one or more I/O driver models; providing a simulated bus for transferring signals between said I/O controller and said switch; storing a test case comprising computer-executable instructions on an external memory device; providing a test operating system for controlling said switch; simulating said integrated circuit design by running said test case on said test operating system; and wherein said external memory mapped test device is a software module, said simulated I/O cores and said simulated I/O controller are software descriptions of said integrated circuit design and said external memory mapped test device, said simulated I/O cores and said simulated I/O controller and said test case are executable by said test operating system on an embedded processor to perform verification of said integrated circuit design. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method, comprising:
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loading code representing a computer simulation model of an integrated circuit design into a memory unit, said computer simulation model of said integrated circuit design including simulated I/O cores, a simulated memory controller, a simulated I/O controller, a simulated bus system and a simulated processor, said simulated I/O cores and said simulated I/O controller connected to said simulated processor by said simulated system bus; loading into said memory unit, code representing (i) an external memory model connected to a simulated external memory mapped test device and to said simulated memory controller, (ii) one or more first external I/O driver models connected between said simulated I/O cores and said simulated external memory mapped test device and (iii) one or more second external I/O driver models connected between a simulated switch of said simulated external memory mapped test device and said simulated I/O controller, said simulated switch programmably connectable to said one or more second external I/O driver models in response to computer-executable instructions in a test case, all said connections of (i), (ii) and (iii) by corresponding simulated I/O buses; loading said test case into said processor, said test case comprising said list of computer-executable instructions for said simulated processor into said external memory model, said instructions describing selection of one or more simulated I/O cores and corresponding second external I/O models, allocation of pins of said I/O controller to selected simulated I/O cores and switch positions of said simulated switch to connect said corresponding second external I/O models to said I/O controller; executing said test case on said process and allocating and connecting I/O pins of said simulated I/O controller to one or more of said simulated I/O cores, and connecting said simulated external memory mapped test device to said simulated I/O controller through said corresponding second external I/O models executing test stimuli of said test case on said simulated processor in order to generate data representing a response of said computer simulation model of said integrated circuit design to said test case; outputting said data representing (iv) a response of said computer simulation model of said integrated circuit design to said test case to a computer readable media or a computer, (v) displaying said data representing a response of said computer simulation model of said integrated circuit design on a computer screen, or both (iv) and (v). - View Dependent Claims (9, 10, 11, 12, 13)
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Specification