Resetting of multiple processors in an electronic device

• US 7,917,812 B2
• Filed: 09/30/2006
• Issued: 03/29/2011
• Est. Priority Date: 09/30/2006
• Status: Expired due to Fees

• Current Assignee: Codman Neuro Sciences Sarl
• Original Assignee: Codman Neuro Sciences Sarl
• Inventors: Ginggen, Alec, Crivelli, Rocco
• Primary Examiner(s): Iqbal; Nadeem
• Application Number:
  US11/541,171
• Publication Number:
  US 20080155359A1
• Time in Patent Office: 1,641 Days
• Field of Search: None
• US Class Current: 714/55
• CPC Class Codes: G06F 1/24 Resetting means

Abstract

Automatic resetting of a group of multiple processors in an electronic device wherein the processors are arranged in either a cascade chain or master-slave configuration. Upon the receipt of an originating reset signal by any one of the multiple processors the remaining processors are reset upon receipt of a forced reset signal generated by one of the processors in the group. The system states prior to the originating reset of each processor is refreshed to ensure compatible synchronization of system states and thus proper communication among the processors.

Claims

1. A device comprising:

multiple processors forming a group, one processor in the group being reboot upon receiving an originating reset signal and the remaining processors in the group each being reboot upon receiving an automatically invoked forced reset signal from at least one of the multiple processors, wherein the one processor in the group that receives the originating reset signal also receives a bypass signal along with the forced reset signal from at least one of the other multiple processors in the group.

2. The device in accordance with claim 1, wherein the multiple processors are connected in a cascade chain to include a first processor and a last processor.

3. The device in accordance with claim 2, wherein each of the multiple processors includes circuitry for transmitting the forced reset signal from one processor in the chain to only one other processor in the chain upon receiving an originating reset signal or a forced reset signal.

4. The device in accordance with claim 1, wherein the plural processors include one master processor and at least one slave processor.

5. The device in accordance with claim 4, wherein the master processor includes circuitry for transmitting the forced reset signal to each slave processor in the group that does not receive the originating reset signal, and each slave processor includes circuitry for transmitting the forced reset signal to the master processor.

6. The device in accordance with claim 1, wherein the device includes at least three processors.

7. The device in accordance with claim 1, wherein each of the multiple processors includes an associated watchdog circuit for detecting an error condition and circuitry for generating an originating reset signal upon the detection of the error condition.

8. The device in accordance with claim 1, further comprising a non-volatile memory device for storing systems states of each of the multiple processors prior to the originating reset signal, the multiple processors being refreshed by the stored system states to that prior to the originating reset signal to achieve synchronization of compatible system states among the multiple processors.

9. The device in accordance with claim 1, further comprising multiple non-volatile memory devices, one associated with each of the multiple processors, each of the non-volatile memory devices storing a system state of another processor in the group prior to the originating reset signal, the system state of each of the multiple processors in the group being refreshed by the stored system states to that prior to the originating reset signal to achieve synchronization of compatible system states among the multiple processors.

10. The device in accordance with claim 1, wherein the originating reset signal is triggered in response to one of multiple sources of reset including detection of an error signal.

11. A method for automatically resetting of all processors in an electronic device including multiple processors configured in a cascade chain including a first processor and a last processor, comprising the steps of:

starting with the processor that receives an originating reset signal, each processor automatically transmitting a forced reset signal to the next processor downstream in the chain; and

upon the last processor in the chain receiving a forced reset signal, starting with the last processor, each processor transmitting a pair of signals to the previous processor upstream in the chain until the first processor receives the pair of signals, the pair of signals including a forced reset signal and a bypass signal.

12. The method in accordance with claim 11, further comprising the steps of:

retrieving from a non-volatile memory device stored system states of the processors prior to the originating reset signal; and

refreshing in each of the multiple processors the respective retrieved system states to ensure synchronization of compatible system states among the multiple processors.

13. The method in accordance with claim 12, further comprising the step of providing an appropriate instruction after reset to at least one processor based on an origin of reset of another processor in the chain.

14. The method in accordance with claim 13, wherein the instruction provided to the first processor in the chain is based on the origin of reset of the last processor in the chain.

15. The method in accordance with claim 13, wherein the originating reset signal is triggered in response to one of multiple sources of reset including detection of an error signal.

16. A method for automatically resetting of all processors in an electronic device including multiple processors including one master processor and at least one slave processor, comprising the steps of:

transmitting to each slave processor that has not received an originating reset signal a forced reset signal generated by the master processor; and

transmitting a pair of signals from each slave processor to the master processor, the pair of signals including a forced reset signal and a bypass signal.

17. The method in accordance with claim 16, further comprising the step of:

retrieving from a non-volatile memory device system states of each of the multiple processors prior to the originating reset; and

refreshing in each of the multiple processors the retrieved system states to ensure synchronization of compatible system states among the multiple processors.

18. The method in accordance with claim 16, further comprising the step of providing appropriate instruction after reset to at least one processor based on an origin of reset of another processor in the group.

19. The method in accordance with claim 18, wherein the instructions are provided to the master processor based on the origin of reset of one of the slave processors.

20. The method in accordance with claim 16, wherein the originating reset signal is triggered in response to one of multiple sources of reset including detection of an error signal.