Resetting of multiple processors in an electronic device
First Claim
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1. A device comprising:
- multiple processors forming a group, one processor in the group being reboot upon receiving an originating reset signal and the remaining processors in the group each being reboot upon receiving an automatically invoked forced reset signal from at least one of the multiple processors, wherein the one processor in the group that receives the originating reset signal also receives a bypass signal along with the forced reset signal from at least one of the other multiple processors in the group.
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Abstract
Automatic resetting of a group of multiple processors in an electronic device wherein the processors are arranged in either a cascade chain or master-slave configuration. Upon the receipt of an originating reset signal by any one of the multiple processors the remaining processors are reset upon receipt of a forced reset signal generated by one of the processors in the group. The system states prior to the originating reset of each processor is refreshed to ensure compatible synchronization of system states and thus proper communication among the processors.
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Citations
20 Claims
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1. A device comprising:
multiple processors forming a group, one processor in the group being reboot upon receiving an originating reset signal and the remaining processors in the group each being reboot upon receiving an automatically invoked forced reset signal from at least one of the multiple processors, wherein the one processor in the group that receives the originating reset signal also receives a bypass signal along with the forced reset signal from at least one of the other multiple processors in the group. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for automatically resetting of all processors in an electronic device including multiple processors configured in a cascade chain including a first processor and a last processor, comprising the steps of:
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starting with the processor that receives an originating reset signal, each processor automatically transmitting a forced reset signal to the next processor downstream in the chain; and upon the last processor in the chain receiving a forced reset signal, starting with the last processor, each processor transmitting a pair of signals to the previous processor upstream in the chain until the first processor receives the pair of signals, the pair of signals including a forced reset signal and a bypass signal. - View Dependent Claims (12, 13, 14, 15)
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16. A method for automatically resetting of all processors in an electronic device including multiple processors including one master processor and at least one slave processor, comprising the steps of:
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transmitting to each slave processor that has not received an originating reset signal a forced reset signal generated by the master processor; and transmitting a pair of signals from each slave processor to the master processor, the pair of signals including a forced reset signal and a bypass signal. - View Dependent Claims (17, 18, 19, 20)
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Specification