System and method for circuit schematic generation

• US 7,917,877 B2
• Filed: 05/09/2008
• Issued: 03/29/2011
• Est. Priority Date: 05/09/2008
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: O'Riordan, Donald, Deshpande, Devendra Ramakant, Goel, Alka, Arsintescu, Bogdan George, Singh, Balvinder
• Primary Examiner(s): Whitmore; Stacy A
• Assistant Examiner(s): Dimyan; Magid Y
• Application Number:
  US12/118,558
• Publication Number:
  US 20090282379A1
• Time in Patent Office: 1,054 Days
• Field of Search: 716/8, 716/12, 716/118, 716/119, 716/126
• US Class Current: 716/118
• CPC Class Codes: G06F 2111/12 Symbolic schematics
• CPC Class Codes: G06F 30/18 Network design, e.g. design based on topological or interconnect aspects of utility systems, piping, heating ventilation air conditioning [HVAC] or cabling circuit design at the physical level G06F30/39; network planning tools for wireless communication networks H04W16/18
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

The present invention provides a system and method for generating circuit schematic that includes extracting connectivity data of a plurality of devices from a netlist, categorizing the plurality of devices into groups, placing Schematic Analog Placement Constraints on all the instances by identifying instances among the groups that match with a circuit template (in-built as well as user-specified), creating a BFS instance tree of tree instances, creating a two terminal device clusters and creating instance attachments. Using the constraints during grid based placement and eventually generated schematic which look like analog schematic.

Claims

1. A method for generating a circuit schematic, comprising:

using a computer system to identify a first group of instances that match a circuit template;

defining placement and constraint data for instances of the first group;

creating a circuit schematic having a grid by placing instances of the firstgroup in the grid based on the placement and constraint data; and

routing the instances of the first group using the placement and constraint data.

2. The method of claim 1, wherein defining placement and constraint data further comprising:

specifying a pair of master devices;

specifying a number of terminal pairs of instances;

specifying a quadrant based relative position information of instance pairs;

specifying orientation information for instance pairs; and

specifying augmentation information for instance pairs.

3. The method of claim 2, wherein defining placement and constraint data further comprising creating a topology cluster based on a topology specification template.

4. The method of claim 2, wherein specifying the pair of master devices of instances comprises one or more of a n-type MOSFET transistor device (NMOS), a p-type MOSFET transistor device (PMOS), a NPN bipolar transistor device (NTX), and a PNP bipolar transistor device (PTX).

5. The method of claim 2, wherein creating the topology cluster further comprising specifying a number of terminal pairs, wherein a first terminal pair belongs to the first instance and a second terminal pair belongs to a second instance.

6. The method of claim 2, wherein creating the topology cluster further comprising specifying a quadrant based location to instances matching the pair of master devices and the number of terminal pairs.

7. The method of claim 2, wherein creating the topology cluster further comprising specifying orientation information to instances matching the pair of master devices and the number of terminal pairs.

8. The method of claim 2, wherein creating the topology cluster further comprising specifying augmentation information to instances matching the pair of master devices and the number of terminal pairs.

9. The method of claim 8, wherein the augmentation information comprises:

NONE, HORIZONTAL, VERTICAL, DIAGONAL, or Darington Pair augmentation information.

10. The method of claim 1, wherein the circuit template comprises a built-in template.

11. The method of claim 1, wherein identifying the first group of instances further comprising extracting connectivity data of the first group of instances from a netlist that match the circuit template.

12. The method of claim 1, wherein the column of a topology cluster is placed probabilistically in a schematic placement grid, and wherein each cluster is assigned a row based on a relative placement in the topology cluster.

13. The method of claim 1, wherein defining placement and constraint data comprises:

identifying a second group of instances that contains only two-terminal devices;

clustering the identified two-terminal devices; and

creating a dummy instance for each clustered two-terminal devices.

14. The method of claim 13, wherein a two terminal device is a device having only two terminals with each terminal in opposite direction.

15. The method of claim 14, wherein for each two-terminal instance cluster, a dummy instance is created, wherein dummy ports of a dummy instance are created for each net that connects to an instance which does not belong to the same two-terminal cluster.

16. The method of claim 14, wherein for each two-terminal cluster, the instances and their connections belonging to this cluster are removed from the instance and connectivity lists, respectively.

17. The method of claim 14, wherein the dummy instance and dummy port connections for each cluster are inserted in the instance and instance connection list, respectively.

18. The method of claim 13, the cluster of two terminal devices comprises:

a resistor-capacitor circuit or a series-parallel circuit cluster (SPC).

19. The method of claim 18, wherein the SPC cluster is created by first finding parallel instances and expanding the parallel instances in a direction of a port.

20. The method of claim 19, wherein expanding the parallel instances comprises:

adding a two terminal instance in series on one side of the SPC cluster.

21. The method of claim 18, wherein while creating cluster of two terminal instances, each instance is assigned relative row and column values.

22. The method of claim 1, wherein defining placement and constraint data further comprising creating a breadth-first search (BFS) tree.

23. The method of claim 22, wherein creating the breadth-first search (BFS) tree further comprising identifying instances in the first group having a top port being connected to a power net, wherein the identified instances are added at the level zero of the breadth-first search (BFS) tree.

24. A computer system for generating a circuit schematic, the computer system comprising:

a processor;

a memory connected to the processor; and

a non-transitory computer readable medium having instructions embedded therein, the instructions configured to cause the processor to perform the operations of;

identifying a first group of instances that match a circuit template;

defining placement and constraint data for instances of the first group;

creating a circuit schematic having a grid by placing instances of the first group in the grid based on the placement and constraint data; and

routing the instances of the first group using the placement and constraint data.