Memory cell and method of forming a magnetic tunnel junction (MTJ) of a memory cell

• US 7,919,794 B2
• Filed: 01/08/2008
• Issued: 04/05/2011
• Est. Priority Date: 01/08/2008
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Nowak, Matt, Kang, Seung H., Gu, Shiqun
• Primary Examiner(s): Richards; N Drew
• Assistant Examiner(s): DIALLO, MAMADOU L
• Application Number:
  US11/970,557
• Publication Number:
  US 20090174015A1
• Time in Patent Office: 1,183 Days
• Field of Search: 257 68- 71, 257296-309, 257905-908, 257E27084-E27097, 257/E27.075
• US Class Current: 257/241
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices

Abstract

A memory including a memory cell and method for producing the memory cell are disclosed. The memory includes a substrate in a first plane. A first metal connection extending in a second plane is provided. The second plane is substantially perpendicular to the first plane. A magnetic tunnel junction (MTJ) is provided having a first layer coupled to the metal connection such that the first layer of the MTJ is oriented along the second plane.

Claims

1. A memory comprising:

a substrate in a first plane;

a first metal connection extending in a second plane, wherein the second plane is substantially perpendicular to the first plane;

a first magnetic tunnel junction (MTJ) having a first layer, a second layer and a third layer, the first layer being coupled to the first metal connection, such that the first layer of the MTJ is oriented along the second plane, wherein the second and third layers are also oriented along the second plane; and

a first metal via extending in a second plane offset from the first metal connection and coupled to the third layer of the first MTJ and configured to direct current flow in a direction oriented along the first plane, between the first connection and first via through the first, second and third layers of the first MTJ.

2. The memory of claim 1, wherein a transistor is formed on the substrate.

3. The memory of claim 2, wherein the first metal connection is coupled to the transistor.

4. The memory of claim 3, further comprising:

a source line connection and a word line connection, wherein each are coupled to the transistor.

5. The memory of claim 4, further comprising:

a bit line connection coupled to the first metal via of the first MTJ.

6. The memory of claim 5, wherein the current is configured to flow between the bit line connection and the metal connection through the layers of the first MTJ in the second plane.

7. The memory of claim 1, wherein the first layer is a pinned layer, the second layer is a tunnel barrier layer and the third layer is a free layer.

8. The memory of claim 7, further comprising:

a trench formed in an insulator, wherein the pinned, tunnel barrier, and free layers of the first MTJ are formed in the trench,

wherein the trench has a bottom portion parallel to the first plane and a sloped portion sloped with respect to the second plane, and

wherein at least the tunnel barrier layer is thicker in the bottom portion and sloped portion than a portion oriented along the second plane.

9. The memory of claim 1, further comprising:

a second metal connection extending in the second plane; and

a second magnetic tunnel junction (MTJ) having a first layer coupled to the second metal connection such that the first layer of the second MTJ is oriented along the second plane.

10. The memory of claim 9, wherein one source line is shared for each pair of the MTJs.

11. The memory of claim 10, further comprising:

a first word line for the first MTJ; and

a second word line for the second MTJ.

12. The memory of claim 11, wherein the first word line is positioned between the first metal connection and a source line connection, and wherein the second word line is positioned between the second metal connection and the source line connection.

13. The memory of claim 9, wherein the first MTJ is located on a first side of the first metal connection and wherein the second MTJ is located on a side of the second metal connection that is adjacent the first side of the first metal connection.

14. The memory of claim 1, wherein the memory is a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM).

20. The memory of claim 1, further comprising:

a third means for conducting extending in the vertical plane; and

a second storage means having a first layer coupled to the third means for conducting such that the first layer of the second storage means is disposed on vertical surface of the third conducting means.

21. The memory of claim 20, further comprising:

a first word line for the first storage means; and

a second word line for the second storage means, wherein one source line is shared for each pair of the storage means.

15. A memory comprising:

a substrate in a horizontal plane;

a first means for conducting extending vertically from the horizontal plane in a vertical plane that is substantially perpendicular to the horizontal plane;

a first storage means having a first layer, a second layer and a third layer, the first layer being disposed on a vertical surface of the first means for conducting at a vertical interface, wherein the first storage means is a magnetic tunnel junction (MTJ); and

a second means for conducting extending vertically, offset from the first conducting means, and coupled to the third layer of the first storage means that is disposed in the vertical plane, and

wherein the first, second and third layers and first and second means for conducting are configured to direct current flow in a direction oriented along the horizontal plane through the first, second and third layers of the first storage means.

16. The memory of claim 15, wherein a means for controlling electrical current is formed on the substrate.

17. The memory of claim 16, further comprising:

a source line connection and a word line connection, wherein each are coupled to the means for controlling electrical current and wherein the first means for conducting is coupled to the means for controlling electrical current.

18. The memory of claim 15, wherein the first layer is a pinned layer the second layer is a tunnel barrier layer and the third layer is a free layer.

19. The memory of claim 18, further comprising:

a trench formed in an insulator, wherein the pinned, tunnel barrier, and free layers of the first storage means are formed in the trench,

wherein the trench has a bottom portion parallel to the horizontal plane and a sloped portion sloped with respect to the horizontal plane, and

wherein at least the tunnel barrier layer is thicker in the bottom portion and sloped portion than a portion vertically disposed in the vertical plane.

22. The memory of claim 15, wherein the memory is a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM).