Tier structure with tier frame having a feedthrough structure

• US 7,919,844 B2
• Filed: 09/20/2006
• Issued: 04/05/2011
• Est. Priority Date: 05/26/2005
• Status: Active Grant

• Current Assignee: Nytell Software LLC (Intellectual Ventures LLC)
• Original Assignee: Aprolase Development Co LLC (Intellectual Ventures LLC)
• Inventors: Stern, Jonathan, Ozguz, Volkan
• Primary Examiner(s): Louie; Wai-Sing
• Assistant Examiner(s): Jahan; Bilkis
• Application Number:
  US11/524,090
• Publication Number:
  US 20070035033A1
• Time in Patent Office: 1,658 Days
• Field of Search: 257/666, 257/686, 257/676, 257/778, 257/784, 257/E25.023, 257/621, 257/774, 257/E21.597, 438/629, 438/630, 438637-640, 438/668, 438/672, 438/675
• US Class Current: 257/686
• CPC Class Codes: H01L 21/4803 Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks H01L21/4846 takes precedence; printed circuit boards H05K1/00
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/32188 the layer connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1094 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/3672 Foil-like cooling fins or heat sinks being part of lead-frames H01L23/49568
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/52 Arrangements for conducting electric current within the device in operation from one component to another , i.e. interconnections, e.g. wires, lead frames optical interconnections G02B6/00
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07811 : Extrinsic, i.e. with electrical conductive fillers
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15312 : being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/1627 : stacked type assemblies, e.g. stacked multi-cavities
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A stackable tier structure comprising one or more integrated circuit die and one or more feedthrough structures is disclosed. The I/O pads of the integrated circuit die are electrically rerouted using conductive traces from the first side of the tier structure to a feedthrough structure comprising one ore more conductive structures. The conductive structures electrically route the integrated die pads to predetermined locations on the second side of the tier structure. The predetermined locations, such as exposed conductive pads or conductive posts, in turn, may be interconnected to a second tier structure or other circuitry to permit the fabrication of a three-dimensional microelectronic module comprising one or more stacked tiers.

Claims

1. A tier structure comprising:

a tier frame including a first tier side, a second tier side, a feedthrough structure, and an integrated circuit die comprising an I/O pad, wherein the feedthrough structure comprises a conductive structure including a photoresist, wherein the conductive structure is configured to route electrical signals through the tier frame, and wherein the I/O pad is electrically connected to the conductive structure by a conductive trace; and

an exposed electrically-conductive pad disposed on the first or second tier side, wherein the exposed electrically-conductive pad is electrically connected to the conductive structure.

2. The tier structure of claim 1, wherein the tier frame further comprises a molded dielectric material.

3. The tier structure of claim 1, wherein the tier frame further comprises a polyimide material.

4. The tier structure of claim 1, wherein the conductive structure comprises a metallized polymer column.

5. The tier structure of claim 4, wherein the metallized polymer column comprises an anisotropic conductive film.

6. The tier structure of claim 4, wherein the metallized polymer column comprises an anisotropic conductive paste.

7. The tier structure of claim 1, wherein the tier frame further comprises silicon, and wherein the conductive structure comprises a conductive via defined in the tier frame.

8. The tier structure of claim 7, wherein the silicon has a resistivity greater than 100 ohms per centimeter.

9. The tier structure of claim 1, further comprising an aperture configured to receive the feedthrough structure.

10. The tier structure of claim 1, wherein the exposed electrically-conductive pad is electrically connected to the conductive structure by the conductive trace.

11. A tier structure comprising:

a prefabricated tier frame including a first tier side, a second tier side, a prefabricated feedthrough structure, and a prefabricated integrated circuit die comprising an I/O pad, wherein the prefabricated feedthrough structure comprises a conductive structure including a photoresist, wherein the conductive structure is configured to route electrical signals through the tier frame, and wherein the I/O pad is electrically connected to the conductive structure by a conductive trace; and

an exposed electrically-conductive pad disposed on the first or second tier side, wherein the exposed electrically-conductive pad is electrically connected to the conductive structure.

12. The tier structure of claim 11, wherein the prefabricated tier frame further comprises molded dielectric material.

13. The tier structure of claim 11, wherein the prefabricated tier frame further comprises a polyimide material.

14. The tier structure of claim 11, wherein the conductive structure comprises a prefabricated metallized polymer column.

15. The tier structure of claim 11, wherein the prefabricated tier frame further comprises silicon, and wherein the conductive structure comprises a conductive via defined in the prefabricated tier frame.

16. The tier structure of claim 11, wherein the exposed electrically-conductive pad is electrically connected to the conductive structure by the conductive trace.

17. A tier structure comprising:

a tier frame including a first tier side, a second tier side, a feedthrough structure, and an integrated circuit die comprising an I/O pad, wherein the feedthrough structure comprises a conductive structure including a photoresist, wherein the conductive structure is configured to route electrical signals through the tier frame, and wherein the I/O pad is electrically connected to the conductive structure by a conductive trace; and

an exposed electrically-conductive pad disposed on the first or second tier side, wherein the exposed electrically-conductive pad is electrically connected to the conductive structure by the conductive trace.

18. The tier structure of claim 17, wherein the tier frame further comprises a molded dielectric material.

19. The tier structure of claim 17, wherein the tier frame further comprises a polyimide material.

20. The tier structure of claim 17, wherein the conductive structure comprises a metallized polymer column.

21. The tier structure of claim 20, wherein the metallized polymer column comprises an anisotropic conductive film or an anisotropic conductive paste.

22. The tier structure of claim 17, wherein the tier frame further comprises silicon and wherein the conductive structure comprises a conductive via defined in the tier frame.

23. The tier structure of claim 17, further comprising an aperture configured to receive the feedthrough structure.

24. A stack comprising:

a first tier structure including a first tier frame that comprises a first tier side, a second tier side, a first feedthrough structure, and a first integrated circuit die that comprises a first I/O pad, wherein the first feedthrough structure comprises a first conductive structure configured to route electrical signals from the first or second tier side through the first tier frame, wherein the first conductive structure includes a photoresist, and wherein the first I/O pad is electrically connected to the first conductive structure by a first conductive trace;

a second tier structure including a second tier frame that comprises a third tier side, a fourth tier side, a second feedthrough structure, and a second integrated circuit die that comprises a second I/O pad, wherein the second feedthrough structure comprises a second conductive structure configured to route electrical signals from devices on the third or fourth tier side through the second tier frame, and wherein the second I/O pad is electrically connected to the second conductive structure by a second conductive trace;

a first exposed electrically-conductive pad electrically connected to the first conductive structure and disposed on the first or second tier side;

a second electrically-conductive pad electrically connected to the second conductive structure and disposed on the third or fourth tier side; and

a third conductive structure configured to electrically connect the first I/O pad to the second I/O pad.

25. The stack of claim 24, wherein the third conductive structure comprises an anisotropic conductive film.

26. The stack of claim 24, wherein the third conductive structure comprises an anisotropic conductive paste.

27. The stack of claim 24, wherein the third conductive structure comprises a metallized polymer column.

28. The stack of claim 24, wherein the third conductive structure comprises a stacked stud bump column including a plurality of stacked stud bumps.

29. The stack of claim 24, further comprising a thermal management layer between the first and second tier structures.

30. The stack of claim 24, further comprising a copper shim between the first and second tier structures.