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Chip structure and process for forming the same

  • US 7,919,867 B2
  • Filed: 02/02/2008
  • Issued: 04/05/2011
  • Est. Priority Date: 12/13/2001
  • Status: Expired due to Fees
First Claim
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1. A chip comprising:

  • a silicon substrate;

    a transistor in or on said silicon substrate;

    a first metal layer over said silicon substrate;

    a second metal layer over said first metal layer and over said silicon substrate;

    a dielectric layer between said first and second metal layers;

    a conductive pad over said silicon substrate;

    a passivation layer over said silicon substrate, over said first and second metal layers and over said dielectric layer, wherein said passivation layer comprises a nitride, wherein a first opening in said passivation layer is over a first contact point of said conductive pad, and said first contact point is at a bottom of said first opening;

    a first polymer layer on said passivation layer, wherein said first polymer layer has a thickness between 1 and 100 micrometers;

    a metallization structure on said first contact point and on a top surface of said first polymer layer, wherein said metallization structure comprises a titanium-containing layer on said first contact point and on said top surface, and a gold layer directly on said titanium-containing layer, over said first contact point and over said top surface, wherein said metallization structure is connected to said first contact point through said first opening; and

    a second polymer layer on said metallization structure and on said top surface, wherein a second opening in said second polymer layer is over a second contact point of said metallization structure, and said second contact point is at a bottom of said second opening, wherein said second contact point is connected to said first contact point through said first opening.

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