Chip structure and process for forming the same

• US 7,919,867 B2
• Filed: 02/02/2008
• Issued: 04/05/2011
• Est. Priority Date: 12/13/2001
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan, Huang, Ching-Cheng
• Primary Examiner(s): LOUIE, WAI SING
• Application Number:
  US12/024,999
• Publication Number:
  US 20080122099A1
• Time in Patent Office: 1,158 Days
• Field of Search: 257/643, 257/758, 257/760, 257/763, 257/774
• US Class Current: 257/758
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05073 Single internal layer
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0558 being stacked
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05657 Cobalt [Co] as principal constituent
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 27/0248 : for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.

Claims

1. A chip comprising:

a silicon substrate;

a transistor in or on said silicon substrate;

a first metal layer over said silicon substrate;

a second metal layer over said first metal layer and over said silicon substrate;

a dielectric layer between said first and second metal layers;

a conductive pad over said silicon substrate;

a passivation layer over said silicon substrate, over said first and second metal layers and over said dielectric layer, wherein said passivation layer comprises a nitride, wherein a first opening in said passivation layer is over a first contact point of said conductive pad, and said first contact point is at a bottom of said first opening;

a first polymer layer on said passivation layer, wherein said first polymer layer has a thickness between 1 and 100 micrometers;

a metallization structure on said first contact point and on a top surface of said first polymer layer, wherein said metallization structure comprises a titanium-containing layer on said first contact point and on said top surface, and a gold layer directly on said titanium-containing layer, over said first contact point and over said top surface, wherein said metallization structure is connected to said first contact point through said first opening; and

a second polymer layer on said metallization structure and on said top surface, wherein a second opening in said second polymer layer is over a second contact point of said metallization structure, and said second contact point is at a bottom of said second opening, wherein said second contact point is connected to said first contact point through said first opening.

2. The chip of claim 1, wherein said first polymer layer comprises polyimide.

3. The chip of claim 1, wherein said nitride comprises silicon nitride.

4. The chip of claim 1, wherein said second polymer layer comprises polyimide.

5. The chip of claim 1, wherein said titanium-containing layer comprises a titanium-tungsten-alloy layer.

6. The chip of claim 1, wherein said second metal layer comprises a copper layer.

7. The chip of claim 1, wherein said second metal layer comprises an aluminum layer.

8. A chip comprising:

a silicon substrate;

a transistor in or on said silicon substrate;

a first metal layer over said silicon substrate;

a second metal layer over said first metal layer and over said silicon substrate;

a dielectric layer between said first and second metal layers;

a conductive pad over said silicon substrate;

a passivation layer over said silicon substrate, over said first and second metal layers and over said dielectric layer, wherein said passivation layer comprises a nitride, wherein a first opening in said passivation layer is over a first contact point of said conductive pad, and said first contact point is at a bottom of said first opening;

a first polymer layer on said passivation layer, wherein said first polymer layer has a thickness between 1 and 100 micrometers, wherein a second opening in said first polymer layer is over said first contact point;

a metallization structure on said first contact point, on a first sidewall of said first opening, on a second sidewall of said second opening and on a top surface of said first polymer layer, wherein said metallization structure contacts said first sidewall and said second sidewall, wherein said metallization structure comprises a titanium-containing layer on said first contact point, on said first sidewall, on said second sidewall and on said top surface, wherein said titanium-containing layer contacts said first sidewall and said second sidewall, and a gold layer directly on said titanium-containing layer, over said first contact point and over said top surface, wherein said metallization structure is connected to said first contact point through said first and second opening; and

a second polymer layer on said metallization structure and on said top surface, wherein a third opening in said second polymer layer is over a second contact point of said metallization structure, and said second contact point is at a bottom of said third opening, wherein said second contact point is configured for wirebonding, wherein said second contact point is connected to said first contact point through said first and second openings.

9. The chip of claim 8, wherein said first polymer layer comprises polyimide.

10. The chip of claim 8, wherein said nitride comprises silicon nitride.

11. The chip of claim 8, wherein said second polymer layer comprises polyimide.

12. The chip of claim 8, wherein said titanium-containing layer comprises a titanium-tungsten-alloy layer.

13. The chip of claim 8, wherein said second metal layer comprises a copper layer.

14. The chip of claim 8, wherein said second metal layer comprises an aluminum layer.

15. A chip, comprising:

a silicon substrate;

a transistor in or on said silicon substrate;

a first metal layer over said silicon substrate;

a second metal layer over said first metal layer and over said silicon substrate;

a dielectric layer between said first and second metal layers;

a conductive pad over said silicon substrate;

a passivation layer over said silicon substrate, over said first and second metal layers and over said dielectric layer, wherein said passivation layer comprises a topmost insulating nitride of said chip, wherein a first opening in said passivation layer is over a first contact point of said conductive pad, and said first contact point is at a bottom of said first opening;

a metallization structure on said first contact point and over said passivation layer, wherein said metallization structure comprises a titanium-containing layer on said first contact point and over said passivation layer, and a gold layer directly on said titanium-containing layer, over said first contact point and over said passivation layer, wherein said metallization structure is connected to said first contact point through said first opening; and

a first polymer layer on said metallization structure and over said passivation layer, wherein a second opening in said first polymer layer is over a second contact point of said metallization structure, and said second contact point is at a bottom of said second opening, wherein said second contact point is connected to said first contact point through said first opening.

16. The chip of claim 15, wherein said first polymer layer comprises polyimide.

17. The chip of claim 15, wherein said topmost insulating nitride of said chip comprises silicon nitride.

18. The chip of claim 15 further comprising a second polymer layer on said passivation layer, wherein said metallization structure is further on a top surface of said second polymer layer.

19. The chip of claim 15, wherein said titanium-containing layer comprises a titanium-tungsten-alloy layer.

20. The chip of claim 15, wherein said second metal layer comprises a copper layer.

21. A chip comprising:

a silicon substrate;

a transistor in or on said silicon substrate;

a first copper layer over said silicon substrate;

a second copper layer over said silicon substrate;

a dielectric layer between said first and second copper layers;

a copper plug in said dielectric layer and between said first and second copper layers, wherein said copper plug connects said first and second copper layers;

a contact pad over said silicon substrate;

a topmost nitride layer of said chip over said silicon substrate and over said first and second copper layers, wherein a first opening in said topmost nitride layer of said chip is over a first contact point of said contact pad, and said first contact point is at a bottom of said first opening, wherein said first opening has a width between 0.5 and 20 micrometers;

a first polymer layer on a first top surface of said topmost nitride layer of said chip, wherein said first polymer layer has a thickness between 1 and 100 micrometers, wherein a second opening in said first polymer layer is over said first opening and over said first contact point; and

an interconnecting structure on a second top surface of said first polymer layer, on a sidewall of said second opening, on said first top surface, on a sidewall of said first opening and on said first contact point, wherein said interconnecting structure is connected to said first contact point through said first and second openings, wherein said interconnecting structure comprises a conductive layer on said first and second top surfaces, on said sidewall of said second opening, on said sidewall of said first opening and on said first contact point, and an electroplated copper layer on said conductive layer, over said first and second top surfaces and over said first contact point.

22. The chip of claim 21 further comprising a second polymer layer on said interconnecting structure.

23. The chip of claim 22, wherein a third opening in said second polymer layer is over a second contact point of said interconnecting structure, and said second contact point is at a bottom of said third opening, wherein said second contact point is connected to said first contact point through said first and second openings.

24. The chip of claim 21, wherein said conductive layer comprises a titanium-containing layer.

25. A chip comprising:

a silicon substrate;

a metallization structure over said silicon substrate, wherein said metallization structure comprises a first copper layer, a second copper layer over said first copper layer and a copper plug between said first and second copper layers, wherein said second copper layer is connected to said first copper layer through said copper plug;

a dielectric layer over said silicon substrate and between said first and second copper layers, wherein said copper plug is in said dielectric layer;

an inorganic layer over said silicon substrate and over said metallization structure, wherein a first opening in said inorganic layer is over a contact point of said metallization structure, and said contact point is at a bottom of said first opening, wherein said first opening has a width between 0.5 and 20 micrometers;

a polymer layer on a first top surface of said inorganic layer, wherein a second opening in said polymer layer is over said contact point;

a first metal layer on said contact point, on said first top surface, in said first and second openings and on a second top surface of said polymer layer, wherein said first metal layer comprises a conductive layer on said contact point, on a sidewall of said first opening, on a sidewall of said second opening and on said first and second top surfaces, and a third copper layer on said conductive layer, over said contact point and over said first and second top surfaces, wherein said first metal layer has a thickness between 1 and 50 micrometers; and

a second metal layer on said first metal layer, over said contact point and over said second top surface, wherein said second metal layer comprises nickel.

26. The chip of claim 25, wherein said inorganic layer comprises a nitride.

27. The chip of claim 25, wherein said conductive layer comprises titanium.