Coaxial through chip connection

• US 7,919,870 B2
• Filed: 11/06/2006
• Issued: 04/05/2011
• Est. Priority Date: 06/14/2005
• Status: Active Grant

• Current Assignee: Cufer Asset Ltd LLC (Intellectual Ventures LLC)
• Original Assignee: Cufer Asset Ltd LLC (Intellectual Ventures LLC)
• Inventors: Trezza, John
• Primary Examiner(s): Stark; Jarrett J
• Application Number:
  US11/556,826
• Publication Number:
  US 20070138562A1
• Time in Patent Office: 1,611 Days
• Field of Search: 257/777, 257/686, 257/E25.006
• US Class Current: 257/777
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2223/6616 Vertical connections, e.g. vias
• CPC Class Codes: H01L 2223/6622 Coaxial feed-throughs in active or passive substrates
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/114 by blanket deposition of the material of the bump connector
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/116 by patterning a pre-deposited material treatment of parts prior to assembly of the devices H01L21/48
• CPC Class Codes: H01L 2224/11912 the bump being used as a mask for patterning other parts
• CPC Class Codes: H01L 2224/13012 in top view
• CPC Class Codes: H01L 2224/13021 the bump connector being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/13083 Three-layer arrangements
• CPC Class Codes: H01L 2224/13084 : Four-layer arrangements
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13166 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/13184 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/1358 : being stacked
• CPC Class Codes: H01L 2224/136 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13609 : Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/16146 : the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16237 : the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/24226 : the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/45111 : Tin (Sn) as principal constituent
• CPC Class Codes: H01L 2224/75 : Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 2224/75305 : comprising protrusions
• CPC Class Codes: H01L 2224/81001 : involving a temporary auxiliary member not forming part of the bonding apparatus
• CPC Class Codes: H01L 2224/81011 : Chemical cleaning, e.g. etching, flux
• CPC Class Codes: H01L 2224/81054 : Composition of the atmosphere
• CPC Class Codes: H01L 2224/81136 : involving guiding structures, e.g. spacers or supporting members
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81204 : with a graded temperature profile
• CPC Class Codes: H01L 2224/81825 : Solid-liquid interdiffusion
• CPC Class Codes: H01L 2224/81894 : Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2224/83102 : using surface energy, e.g. capillary forces
• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06531 : Non-galvanic coupling, e.g. capacitive coupling
• CPC Class Codes: H01L 2225/06534 : Optical coupling
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06555 : Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 2225/06593 : Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 2225/06596 : Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/427 : Cooling by change of state, e.g. use of heat pipes by liquefied gas H01L23/445
• CPC Class Codes: H01L 23/48 : Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/488 : consisting of soldered or bonded constructions bump connectors H01L24/01
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/66 : High-frequency adaptations
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/75 : Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01002 : Helium [He]
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01007 : Nitrogen [N]
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01025 : Manganese [Mn]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01052 : Tellurium [Te]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01S 2301/176 : Specific passivation layers on surfaces other than the emission facet
• CPC Class Codes: H01S 5/02345 : Wire-bonding
• CPC Class Codes: H01S 5/0237 : by soldering
• CPC Class Codes: H01S 5/0422 : with n- and p-contacts on the same side of the active layer
• CPC Class Codes: H01S 5/0425 : Electrodes, e.g. characterised by the structure
• CPC Class Codes: H01S 5/04254 : characterised by the shape
• CPC Class Codes: H01S 5/04257 : having positive and negative electrodes on the same side of the substrate
• CPC Class Codes: H01S 5/183 : having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
• CPC Class Codes: H01S 5/18308 : having a special structure for lateral current or light confinement

Abstract

An integrated circuit chip includes devices formed by doping of a semiconductor on a substrate and at least one post-device formation through-chip via made up of an annulus of insulating material, an annulus of metallization bounding an outer surface of the annulus of insulating material and an annulus of electrically conductive material within the annulus of insulating material, the annulus of metallization and the annulus of electrically conductive material being electrically isolated from each another.

Claims

1. An integrated circuit chip comprising:

a semiconductor material having an outer surface;

a substrate adjacent to the semiconductor material; and

a via extending entirely through the semiconductor material and the substrate, wherein the via includes;

an insulating material extending from beyond the outer surface of the semiconductor material into the semiconductor material along at least a portion of the via, wherein the insulating material extends through only a portion of the substrate;

a first electrically-conductive material extending from beyond the outer surface of the semiconductor material into the substrate and bounding an outer surface of the insulating material; and

a second electrically-conductive material within the insulating material extending from beyond the outer surface of the semiconductor material into the substrate, wherein the first electrically-conductive material and the second electrically-conductive material are electrically isolated.

2. The integrated circuit chip of claim 1, wherein the insulating material forms a first annulus, wherein the first electrically-conductive material forms a second annulus, and wherein the second electrically-conductive material forms a third annulus.

3. The integrated circuit chip of claim 2, further comprising an electronic chip having a contact, wherein the contact is electrically bonded to the first electrically-conductive material or the second electrically-conductive material.

4. The integrated circuit chip of claim 1, wherein the via comprises a malleable material configured to receive a rigid material.

5. The integrated circuit chip of claim 1, wherein the via comprises a rigid material configured to penetrate into a malleable material.

6. The integrated circuit chip of claim 1, wherein the via is one of a plurality of vias on the integrated circuit chip.

7. The integrated circuit chip of claim 6, wherein at least one of the plurality of vias is located near a periphery of the integrated circuit chip.

8. The integrated circuit chip of claim 1, wherein the integrated circuit chip is one of a plurality of stacked chips, and wherein the plurality of stacked chips are electrically coupled.

9. The integrated circuit chip of claim 1, wherein the second electrically-conductive material comprises a rigid material configured to penetrate into a malleable material.

10. The integrated circuit chip of claim 1, wherein the second electrically-conductive material comprises a malleable material configured to receive a rigid material.

11. The integrated circuit chip of claim 1, wherein the first annulus, the second annulus, and the third annulus comprise a rigid material configured to penetrate a malleable material.

12. The integrated circuit chip of claim 1, wherein a width of the insulating material is defined photolithographically.

13. The integrated circuit chip of claim 1, wherein the first electrically-conductive material is connected to a ground plane.

14. The integrated circuit chip of claim 1, wherein the first electrically-conductive material provides inter-chip shielding.

15. The integrated circuit chip of claim 1, wherein the via has a cross-sectional shape that is not substantially a square or a circle.

16. The integrated circuit chip of claim 1, wherein the via further comprises a sidewall, and wherein the sidewall is non-conductive having been formed by sputtering a dielectric material.

17. The integrated circuit chip of claim 1, wherein the second electrically-conductive material bounds a column of semiconductor material.

18. The integrated circuit chip of claim 1, wherein the second electrically-conductive material comprises a solid conductor.

19. The integrated circuit chip of claim 1, wherein the first electrically-conductive material bounds an inner surface of the insulating material, and wherein the second electrically-conductive material is a solid conductor.

20. The integrated circuit chip of claim 1, wherein the via comprises a post configured to penetrate a void of and form an electrical connection with another integrated circuit chip.

21. An integrated circuit chip comprising:

a semiconductor material; and

a via extending entirely through the semiconductor material, wherein the via includes;

an insulating material extending from beyond a surface of the semiconductor material into the semiconductor material, wherein the insulating material extends only part way through the semiconductor material;

a first electrically-conductive material adjacent an outer surface of the insulating material; and

a second electrically-conductive material adjacent an inner surface of the insulating material, wherein the first electrically-conductive material and the second electrically-conductive material are electrically isolated by the insulating material.

22. The integrated circuit chip of claim 21, wherein the insulating material comprises a first annulus, wherein the first electrically-conductive material comprises a second annulus, and wherein the second electrically-conductive material comprises a third annulus.

23. The integrated circuit chip of claim 21, further comprising an electronic chip having a contact that is electrically connected to the first electrically-conductive material or the second electrically-conductive material.

24. The integrated circuit chip of claim 21, wherein the via comprises a malleable material configured to receive a rigid material.

25. The integrated circuit chip of claim 21, wherein the via comprises a rigid material configured to penetrate into a malleable material.

26. The integrated circuit chip of claim 21, wherein the integrated circuit chip is one of a plurality of stacked chips that are electrically coupled.

27. The integrated circuit chip of claim 21, wherein the first electrically-conductive material is connected to a ground plane.

28. The integrated circuit chip of claim 21, wherein the via further comprises a non-conductive sidewall that includes a dielectric material.

29. The integrated circuit chip of claim 21, wherein the second electrically-conductive material surrounds an outer surface of a column of semiconductor material.

30. The integrated circuit chip of claim 21, wherein the second electrically-conductive material comprises a solid conductor.

31. The integrated circuit chip of claim 30, wherein the first electrically-conductive material bounds an inner surface of the insulating material.

32. The integrated circuit chip of claim 21, wherein the via comprises a post configured to penetrate a void of and form an electrical connection with another integrated circuit chip.

33. An integrated circuit chip comprising:

a semiconductor material having an outer surface; and

a via extending entirely through the semiconductor material, wherein the via includes;

an insulating material extending along a portion of the via;

a first electrically-conductive material bounding an outer surface of the insulating material; and

a second electrically-conductive material within the insulating material, wherein the first electrically-conductive material and the second electrically-conductive material are electrically isolated, and wherein the second electrically-conductive material extends from beyond the outer surface of the semiconductor material into the semiconductor material;

wherein the insulating material and the second electrically-conductive material both extend to a first depth in the semiconductor material, and wherein the first depth is less than the thickness of the semiconductor material such that a portion of the via in which the insulating material and the second-electrically conductive material do not extend is configured to receive a coaxial conductor of another chip.

34. The integrated circuit chip of claim 33, wherein the insulating material forms a first annulus, wherein the first electrically-conductive material forms a second annulus, and wherein the second electrically-conductive material forms a third annulus.

35. The integrated circuit chip of claim 33, wherein the insulating material and the first electrically-conductive material extend from above the outer surface of the semiconductor material into the semiconductor material.

36. The integrated circuit chip of claim 33, wherein the integrated circuit chip is one of a plurality of stacked chips that are electrically connected.

37. The integrated circuit chip of claim 33, wherein the first electrically-conductive material is connected to a ground plane.

38. The integrated circuit chip of claim 33, wherein the via further comprises a non-conductive sidewall that includes a dielectric material.

39. The integrated circuit chip of claim 33, wherein the second electrically-conductive material bounds a column of semiconductor material.

40. The integrated circuit chip of claim 33, wherein the second electrically-conductive material comprises a solid conductor.

41. The integrated circuit chip of claim 40, wherein the first electrically-conductive material bounds an inner surface of the insulating material.

42. The integrated circuit chip of claim 33, wherein the first and second electrically-conductive materials and the insulating material comprise a post configured to penetrate a void of and form an electrical connection with another integrated circuit chip.