Field programmable gate array including a non-volatile user memory and method for programming

• US 7,919,979 B1
• Filed: 01/20/2006
• Issued: 04/05/2011
• Est. Priority Date: 01/21/2005
• Status: Expired due to Fees

• Current Assignee: Microsemi SoC Corp. (Microchip Technology Incorporated)
• Original Assignee: Actel Corporation (Microchip Technology Incorporated)
• Inventors: Mason, Martin, Speers, Theodore
• Primary Examiner(s): Barnie; Rexford N
• Assistant Examiner(s): Hammond; Crystal L
• Application Number:
  US11/336,396
• Time in Patent Office: 1,901 Days
• Field of Search: 326 37- 41, 326/47, 326/16, 365/221, 711/163, 714/30, 714/727, 713/182
• US Class Current: 326/41
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/17768 for security
• CPC Class Codes: H03K 19/17772 for powering on or off

Abstract

An integrated circuit includes a programmable logic unit and an on-chip non-volatile memory. A JTAG port, TAP controller circuit, and program/erase control circuitry provide user access to the non-volatile memory for storage of user data. The non-volatile memory may also be used to store device data such as a serial number, product identification number, date code, or security data. Portions of the non-volatile memory may be made unavailable to the user once programmed, while other portions of the non-volatile may remain available for user access.

Claims

1. A programmable logic device integrated circuit comprising:

a programmable logic unit having programmable logic modules and programmable interconnect elements;

a non-volatile memory block having a user data portion responsively coupled to the programmable logic unit, and a device-specific data portion;

a JTAG port;

program/erase control circuitry coupled to the non-volatile memory block and configurable to deny user access to data stored in the device-specific data portion of the non-volatile memory;

a TAP controller circuit coupled between the JTAG port and the program/erase control circuitry; and

a user JTAG port connected between the TAP controller circuit and the programmable logic unit.

2. The programmable logic device of claim 1, wherein the user JTAG port is connected to a portion of the programmable logic unit that is programmed to function as decode logic.

3. The programmable logic device of claim 1, wherein the programmable logic unit is a field programmable gate array programmable logic circuit.

4. The programmable logic device of claim 1, further comprising a non-JTAG input/output connected to the programmable logic unit.

5. The programmable logic device of claim 1, further comprising a read connection between the programmable logic unit and the nonvolatile memory providing address data from the programmable logic unit to the non-volatile memory and read data from the non-volatile memory to the programmable logic unit.

6. The programmable logic device of claim 1 wherein the non-volatile memory block further includes a security-bit portion to store information provided to the program/erase control circuitry to selectively disable a capability to perform external read and write functions to selected portions of the non-volatile memory through the JTAG port.

7. The programmable logic device of claim 1 wherein data stored in the security-bit portion of the non-volatile memory is accessible to a user via the JTAG port and the program/erase control circuitry is configured to allow user access to data stored in the security-bit portion of the non-volatile memory.

8. The programmable logic device of claim 1 wherein the user JTAG port comprises a group of I/O tiles residing on the periphery of the programmable logic unit.

9. The programmable logic device of claim 1 wherein bidirectional access to the JPEG port from the programmable logic unit provides a capability for dynamic reconfiguration of clock conditioning circuits.