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Field programmable gate array including a non-volatile user memory and method for programming

  • US 7,919,979 B1
  • Filed: 01/20/2006
  • Issued: 04/05/2011
  • Est. Priority Date: 01/21/2005
  • Status: Expired due to Fees
First Claim
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1. A programmable logic device integrated circuit comprising:

  • a programmable logic unit having programmable logic modules and programmable interconnect elements;

    a non-volatile memory block having a user data portion responsively coupled to the programmable logic unit, and a device-specific data portion;

    a JTAG port;

    program/erase control circuitry coupled to the non-volatile memory block and configurable to deny user access to data stored in the device-specific data portion of the non-volatile memory;

    a TAP controller circuit coupled between the JTAG port and the program/erase control circuitry; and

    a user JTAG port connected between the TAP controller circuit and the programmable logic unit.

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