Amplifier output stage with extended operating range and reduced quiescent current
First Claim
1. An output driver system that is responsive to a differential input signal to generate a drive current for an output transistor, wherein the output driver system is arranged to dynamically boost the drive current, the output driver system comprising:
- a differential amplifier block that is arranged to generate a first current (I1) in response to the differential input signal, wherein the first current (I1) has a first magnitude corresponding to a sum (I+S), wherein I corresponds to a DC current portion from the differential amplifier block and S corresponds to a signal varying portion from the differential amplifier block;
a first gain block that is arranged to generate a second current (I2) in response to the first current, wherein the second current (I2) has a second magnitude that is related to the first magnitude by a scaling factor;
a threshold detector block that is arranged to generate a control signal in response to a comparison between the first magnitude of the first current (I1) and a threshold level;
a second gain block that is arranged to generate a third current (I3) and that is responsive to the control signal, wherein the third current (I3) has a third magnitude, and wherein the second gain block is arranged such that the third current (I3) is approximately zero when the first magnitude of the first current (I1) is below the threshold level and non-zero when the first magnitude of the first current (I1) is above the threshold level;
a bias current block that is arranged to generate a nominal biasing current (IB) for the output transistor;
a current mirror block that is arranged to generate a fourth current (I4) having a fourth magnitude that is proportional to a difference (I−
S) according to the scaling factor; and
a summer block that is arranged to combine the nominal biasing current (IB), the second current (I2), the third current (I3), and the fourth current (I4) to generate a biasing current (IOUT) for the output transistor, wherein the summer block is arranged such that IOUT=IB+I 2+I3−
I4.
1 Assignment
0 Petitions
Accused Products
Abstract
An output stage of an amplifier circuit includes one or more output transistors that are selectively driven by a boosted drive circuit, where the boosted drive circuit is arranged such that the output range of the amplifier circuit is increased while maintaining reduced quiescent current. The drive signal to each output transistor is selectively increased only when demanded by the output load conditions. The threshold for boosting the drive signal can be adjusted for optimized performance. In one example, a class AB output stage includes a separate drive boost circuit for each output transistor. For this example, each drive boost circuit has a separate threshold for boosting each of the drive signals to the output transistors. The boosting can also be adjusted to optimize the differential input stage and current mirror maximum current requirement while maintaining minimum required bias currents.
45 Citations
24 Claims
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1. An output driver system that is responsive to a differential input signal to generate a drive current for an output transistor, wherein the output driver system is arranged to dynamically boost the drive current, the output driver system comprising:
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a differential amplifier block that is arranged to generate a first current (I1) in response to the differential input signal, wherein the first current (I1) has a first magnitude corresponding to a sum (I+S), wherein I corresponds to a DC current portion from the differential amplifier block and S corresponds to a signal varying portion from the differential amplifier block; a first gain block that is arranged to generate a second current (I2) in response to the first current, wherein the second current (I2) has a second magnitude that is related to the first magnitude by a scaling factor; a threshold detector block that is arranged to generate a control signal in response to a comparison between the first magnitude of the first current (I1) and a threshold level; a second gain block that is arranged to generate a third current (I3) and that is responsive to the control signal, wherein the third current (I3) has a third magnitude, and wherein the second gain block is arranged such that the third current (I3) is approximately zero when the first magnitude of the first current (I1) is below the threshold level and non-zero when the first magnitude of the first current (I1) is above the threshold level; a bias current block that is arranged to generate a nominal biasing current (IB) for the output transistor; a current mirror block that is arranged to generate a fourth current (I4) having a fourth magnitude that is proportional to a difference (I−
S) according to the scaling factor; anda summer block that is arranged to combine the nominal biasing current (IB), the second current (I2), the third current (I3), and the fourth current (I4) to generate a biasing current (IOUT) for the output transistor, wherein the summer block is arranged such that IOUT=IB+I 2+I3−
I4. - View Dependent Claims (2, 3, 4)
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5. An output driver circuit that is responsive to a differential input signal to generate drive currents for first and second output transistors, wherein the output driver circuit is arranged to dynamically boost the drive currents, the output driver circuit comprising:
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a first current mirror circuit that includes a power terminal, a first output terminal arranged to provide a first current (IQ1), a second output terminal arranged to provide a second current (IQ2), and a sense terminal, wherein the first current mirror circuit is arranged to scale the first current (IQ1) according to a scaling factor (SF) relative to a third current (IQ3) sensed at the sense terminal of the first current mirror circuit, and wherein the first current mirror circuit is arranged to match the second current (IQ2) to the third current (IQ3); a first amplifier circuit that includes a positive power terminal coupled to the first output terminal of the first current mirror circuit, a negative power terminal, an input terminal, and an output terminal, wherein the first amplifier circuit is arranged to receive a first portion of the differential input signal at its input terminal, and wherein the first amplifier circuit has a first DC biasing current corresponding to I; a second amplifier circuit that includes a positive power terminal coupled to the sense terminal of the first current mirror circuit, a negative power terminal, an input terminal, and an output terminal, wherein the second amplifier circuit is arranged to receive a second portion of the differential input signal at its input terminal, and wherein the second amplifier circuit has a second DC biasing current also corresponding to I; a resistor circuit that is coupled between the output terminals of the first and second amplifier circuits, wherein the resistor circuit is arranged to cooperate with the first amplifier circuit and the second amplifier circuit such that a current (S) flowing through the resistor circuit corresponds to a signal varying portion from the first and second amplifier circuits; a second current mirror circuit that includes a power terminal, a first output terminal coupled to the negative power terminal of the first amplifier circuit and arranged to provide a fourth current (IQ4), a second output terminal arranged to provide a fifth current (IQ5), and a sense terminal coupled to the negative power terminal of the second amplifier circuit, wherein the second current mirror circuit is arranged to scale the fourth current (IQ4) according to the scaling factor (SF) relative to a sixth current (IQ6) sensed at the sense terminal of the second current mirror circuit, and wherein the second current mirror circuit is arranged to match the fifth current (IQ5) to the sixth current (IQ6); a first drive circuit that includes a first current terminal coupled to the first output terminal of the first current mirror circuit, a second current terminal coupled to the second output terminal of the second current mirror circuit, and a third current terminal coupled to a first control terminal of the first output transistor, wherein the first drive circuit is arranged to drive the first control terminal with a first output current (IB7) that corresponds to IB7=IBP+SF*S+GP(I+S), where IBP is a first nominal biasing current for the first output transistor, and GP(I+S) is a first dynamically varied gain boost that is approximately zero when (I+S) is below a first threshold and non-zero when (I+S) is above the first threshold; and a second drive circuit that includes a first current terminal coupled to the first output terminal of the second current mirror circuit, a second current terminal coupled to the second output terminal of the first current mirror circuit, and a third current terminal coupled to a second control terminal of the second output transistor, wherein the second drive circuit is arranged to drive the second control terminal with a second output current (IB8) that corresponds to IB8=IBN−
SF*S+GN(I−
S), where IBN is a second nominal biasing current for the second output transistor, and GN(I−
S) is a second dynamically varied gain boost that is approximately zero when (I−
S) is below a second threshold and non-zero when (I−
S) is above the second threshold. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. An output driver circuit that is responsive to a differential input signal to generate drive currents for first and second output transistors, wherein the output driver circuit is arranged to dynamically boost the drive currents to the output transistors, the output driver circuit comprising:
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a first amplifier circuit that includes a first positive power terminal arranged to conduct a first amplifier positive supply current (IA1P=I+S) , a first negative power terminal arranged to conduct a first amplifier negative supply current (IA1N=I−
S), and a first input terminal arranged to receive a first portion of the differential input signal;a second amplifier circuit that includes a second positive power terminal arranged to conduct a second amplifier positive supply current (IA2P=I−
S), a second negative power terminal arranged to conduct a second amplifier negative supply current (IA2N=I+S), and a second input terminal arranged to receive a second portion of the differential input signal;a resistor circuit that is coupled between output terminals of the first and second amplifier circuits and that is arranged to conduct an output current corresponding to S, where S corresponds to a signal varying current for the first and second amplifier circuits, and where I corresponds to a DC biasing current for the first and second amplifier circuits; a first drive circuit that is arranged for driving a first control signal (IB7) to a first control terminal of the first output transistor and that is responsive to signals from the first positive power terminal and a first drive circuit input such that IB7=IBP+SF*S+GP(I+S), where IBP is a first nominal biasing signal for the first output transistor, SF is a scaling factor, and GP(I+S), is a first dynamically varied gain boost that is approximately zero when (I+S) is below a first threshold and non-zero when (I+S) is above the first threshold; a second drive circuit that is arranged for driving a second control signal (IB8) to a second control terminal of the second output transistor and that is responsive to signals from the first negative power terminal and a second drive circuit input such that IB8=IBN−
SF*S+GN(I−
S), where IBN is a second nominal biasing current for the second output transistor, and GN(I−
S) is a second dynamically varied gain boost that is approximately zero when (I−
S) is below a second threshold and non-zero when (I−
S) is above the second threshold;a first transistor with a first terminal coupled to a positive power supply node, a control terminal coupled to the second positive power terminal, and a second terminal coupled to the first positive power terminal, wherein the first transistor is arranged to generate a current corresponding to SF*(I−
S);a second transistor with a first terminal coupled to the positive power supply node, a control terminal coupled to the second positive power terminal, and a second terminal coupled to the second drive circuit input, wherein the second transistor is arranged to generate a current corresponding to (I−
S);a third transistor with a first terminal coupled to the positive power supply node, a control terminal coupled to the second positive power terminal, and a second terminal coupled to the second positive power terminal, wherein the third transistor is arranged to sense a current corresponding to (I−
S);a fourth transistor with a first terminal coupled to a negative power supply node, a control terminal coupled to the second negative power terminal, and a second terminal coupled to the first negative power terminal, wherein the fourth transistor is arranged to generate a current corresponding to SF*(I+S); a fifth transistor with a first terminal coupled to the negative power supply node, a control terminal coupled to the second negative power terminal, and a second terminal coupled to the first drive circuit input, wherein the fifth transistor is arranged to generate a current corresponding to (I+S); and a sixth transistor with a first terminal coupled to the negative power supply node, a control terminal coupled to the second negative power terminal, and a second terminal coupled to the second negative power terminal, wherein the sixth transistor is arranged to sense a current corresponding to (I+S). - View Dependent Claims (18, 19, 20)
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21. An apparatus comprising:
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a differential amplifier configured to generate a first current based on a differential input signal; a first gain unit configured to generate a second current by applying a scaling factor to the first current; a second gain unit configured to generate a third current that is approximately zero when a magnitude of the first current is below a threshold level and non-zero when the magnitude of the first current is above the threshold level; a threshold detector configured to compare the magnitude of the first current and the threshold level and to control the second gain unit based on the comparison; a current mirror configured to generate a fourth current based on the scaling factor; a bias current generator configured to generate a fifth current comprising a nominal biasing current for an output transistor; and a summer configured to generate a biasing current for the output transistor using the second, third, fourth, and fifth currents.
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22. An apparatus comprising:
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first and second amplifiers configured to amplify a differential input signal, each amplifier having positive and negative power terminals; first and second drivers configured to drive first and second output transistors, respectively; a first current mirror having a sense terminal coupled to the positive power terminal of the second amplifier, a first output terminal coupled to the positive power terminal of the first amplifier, and a second output terminal coupled to the second driver; a second current mirror having a sense terminal coupled to the negative power terminal of the second amplifier, a first output terminal coupled to the negative power terminal of the first amplifier, and a second output terminal coupled to the first driver; and a resistor coupled between output terminals of the first and second amplifiers. - View Dependent Claims (23, 24)
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Specification