Graphics display system with video scaler

• US 7,920,151 B2
• Filed: 05/26/2009
• Issued: 04/05/2011
• Est. Priority Date: 11/09/1998
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: MacInnis, Alexander G., Tang, Chengfuh Jeffrey, Kranawetter, Greg A., Patterson, James T., Xie, Xiaodong
• Primary Examiner(s): HARRISON, CHANTE E
• Application Number:
  US12/472,235
• Publication Number:
  US 20090295834A1
• Time in Patent Office: 679 Days
• Field of Search: 345/660, 345/667, 345/530, 345/543
• US Class Current: 345/660
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 9/00 Image coding bandwidth or redundancy reduction for static pictures H04N1/41; coding or decoding of static colour picture signals H04N1/64; methods or arrangements for coding, decoding, compressing or decompressing digital video signals H04N19/00
• CPC Class Codes: G06T 9/007 Transform coding, e.g. discrete cosine transform
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 2340/10 Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 2360/02 Graphics controller able to handle multiple formats, e.g. input or output formats
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 2360/126 The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
• CPC Class Codes: G09G 2360/128 Frame memory using a Synchronous Dynamic RAM [SDRAM]
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/02 : characterised by the way in which colour is displayed details of colour display specific for CRTs G09G1/28; specific for flat matrix panels other than liquid crystal displays G09G3/2003; specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 5/024 : using colour registers, e.g. to control background, foreground, surface filling G09G5/06 takes precedence
• CPC Class Codes: G09G 5/026 : Control of mixing and/or overlay of colours in general G09G5/022 and G09G5/024 take precedence
• CPC Class Codes: G09G 5/06 : using colour palettes, e.g. look-up tables
• CPC Class Codes: G09G 5/12 : Synchronisation between the display unit and other units, e.g. other display units, video-disc players
• CPC Class Codes: G09G 5/14 : Display of multiple viewports
• CPC Class Codes: G09G 5/28 : for enhancement of character form, e.g. smoothing
• CPC Class Codes: G09G 5/346 : for systems having a bit-mapped display memory
• CPC Class Codes: G09G 5/36 : characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
• CPC Class Codes: G09G 5/363 : Graphics controllers
• CPC Class Codes: H04N 11/143 : Encoding means therefor H04N11/16 takes precedence
• CPC Class Codes: H04N 11/20 : Conversion of the manner in which the individual colour picture signal components are combined, e.g. conversion of colour television standards
• CPC Class Codes: H04N 19/42 : characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 : characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/436 : using parallelised computational arrangements
• CPC Class Codes: H04N 19/44 : Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/59 : involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution
• CPC Class Codes: H04N 19/61 : in combination with predictive coding
• CPC Class Codes: H04N 21/42204 : User interfaces specially adapted for controlling a client device through a remote control device; Remote control devices therefor constructive details of casings for the remote control device H01H9/0235; user interfaces for controlling a tuning device of a television receiver through a remote control H03J9/00; remote control of peripheral devices connected to a television receiver through the remote control device of the television receiver H04B1/205
• CPC Class Codes: H04N 21/426 : Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/42653 : for processing graphics
• CPC Class Codes: H04N 21/4305 : Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/4316 : for displaying supplemental content in a region of the screen, e.g. an advertisement in a separate window
• CPC Class Codes: H04N 21/434 : Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream demultiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04N 21/440263 : by altering the spatial resolution, e.g. for displaying on a connected PDA
• CPC Class Codes: H04N 21/4438 : Window management, e.g. event handling following interaction with the user interface
• CPC Class Codes: H04N 21/47 : End-user applications
• CPC Class Codes: H04N 5/04 : Synchronising for television systems using pulse code modulation H04N7/56
• CPC Class Codes: H04N 5/126 : whereby the synchronisation signal indirectly commands a frequency generator
• CPC Class Codes: H04N 5/14 : Picture signal circuitry for video frequency region cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00
• CPC Class Codes: H04N 5/44504 : Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits
• CPC Class Codes: H04N 5/45 : Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen
• CPC Class Codes: H04N 5/46 : for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27
• CPC Class Codes: H04N 7/0122 : the input and the output signals having different aspect ratios
• CPC Class Codes: H04N 7/0135 : involving interpolation processes interpolation-based image scaling G06T3/4007; interpolation for video coding H04N19/587, H04N19/59
• CPC Class Codes: H04N 9/45 : Generation or recovery of colour sub-carriers
• CPC Class Codes: H04N 9/641 : Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence
• CPC Class Codes: H04N 9/642 : Multi-standard receivers

Abstract

A video processing device may comprise one or more processors and/or circuits for use in a video processing device, in which the one or more processors and/or circuits may comprise a video scaler, a memory, a scaler engine, a clock selection circuit. The one or more processors and/or circuits are operable to receive a video image and select a video input clock or a display output clock for upscaling the received video image, or select the video input clock or the display output clock for downscaling the received video image based on a determination of whether the video image is to be downscaled or upscaled. The one or more circuits may be operable to downscale the received video image to generate a first scaled video image, and/or upscale the received video image to generate a second scaled video image, based on the selection.

Claims

1. A system for processing video, the system comprising:

one or more processors and/or circuits for use in a video processing device, said one or more processors and/or circuits comprise a video scaler, a memory, a scaler engine, a clock selection circuit, and wherein said one or more processors and/or circuits are operable to;

receive a video image;

select one of a video input clock and a display output clock for upscaling said received video image and/or select one of said video input clock and said display output clock for downscaling said received video image based on a determination of whether said video image is to be downscaled or upscaled;

downscale said received video image to generate a first scaled video image based on said selection and/or upscale said received video image to generate a second scaled video image based on said selection; and

store said received video image and/or said first scaled video image.

2. The system according to claim 1, wherein said one or more processors and/or circuits are operable to:

receive said video image to be upscaled from an input of said video scaler;

receive said first scaled video image from said scaler engine; and

communicate said video image to be upscaled or said first scaled video image to said memory.

3. The system according to claim 1, wherein said one or more processors and/or circuits are operable to:

receive the video image to be downscaled from an input of said video scaler;

receive said video image to be upscaled from said memory; and

provide said video image to be downscaled or said video image to be upscaled to said scaler engine.

4. The system according to claim 1, wherein said one or more processors and/or circuits are operable to:

receive said first scaled video image from said memory;

receive said second scaled video image from said scaler engine; and

output either said first scaled video image or said second scaled video image.

5. The system according to claim 1, wherein said one or more processors and/or circuits are operable to:

receive and select between a digital video image and a digitized analog video image; and

output said selected one of said digital video image and said digitized analog video image.

6. The system according to claim 1, wherein said scaler engine downscales said received video image using said video input clock.

7. The system according to claim 1, wherein said scaler engine upscales said video image using said display output clock.

8. The system according to claim 1, wherein said one or more processors and/or circuits comprise a plurality of line buffers that buffers said video image that is an input to said video scaler.

9. The system according to claim 1, wherein said scaler engine comprises a horizontal scaler and a vertical scaler.

10. The system according to claim 1, wherein said scaler engine is a single physical device that is logically in both an upscale path and a downscale path utilized for processing said video image.

11. A method for processing video, the method comprising:

performing by one or more processors and/or circuits in a video processing device, said one or more processors and/or circuits comprising a video scaler, a memory, a scaler engine, a clock selection circuit;

receiving a video image;

selecting one of a video input clock and a display output clock for upscaling said received video image and/or selecting one of said video input clock and said display output clock for downscaling said received video image based on a determination of whether said video image is to be downscaled or upscaled;

downscaling said received video image to generate a first scaled video image based on said selection and/or upscale said received video image to generate a second scaled video image based on said selection; and

storing said received video image and/or said first scaled video image.

12. The method according to claim 11, comprising:

receiving said video image to be upscaled from an input of said video scaler;

receiving said first scaled video image from said scaler engine; and

communicating said video image to be upscaled or said first scaled video image to said memory.

13. The method according to claim 11, comprising:

receiving said video image to be downscaled from an input of said video scaler;

receiving said video image to be upscaled from said memory; and

providing said video image to be downscaled or said video image to be upscaled to said scaler engine.

14. The method according to claim 11, comprising:

receiving said first scaled video image from said memory;

receiving said second scaled video image from said scaler engine; and

outputting either said first scaled video image or said second scaled video image.

15. The method according to claim 11, comprising:

receiving and select between a digital video image and a digitized analog video image; and

outputting said selected one of said digital video image and said digitized analog video image.

16. The method according to claim 11, comprising downscaling said received video image by said scaler engine using said video input clock.

17. The method according to claim 11, comprising upscaling said video image by said scaler engine using said display output clock.

18. The method according to claim 11, wherein said one or more processors and/or circuits comprises a plurality of line buffers that enables buffering of said video image that is an input to said video scaler.

19. The method according to claim 11, wherein said scaler engine comprises a horizontal scaler and a vertical scaler.

20. The method according to claim 11, wherein said scaler engine is a single physical device that is logically in both an upscale path and a downscale path utilized for processing of said video image.