CMOS active pixel sensor with a sample and hold circuit having multiple injection capacitors and a fully differential charge mode linear synthesizer with skew control

• US 7,920,184 B2
• Filed: 01/12/2009
• Issued: 04/05/2011
• Est. Priority Date: 08/13/2002
• Status: Expired due to Term

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Inventors: Rossi, Giuseppe
• Primary Examiner(s): Tran; Sinh
• Assistant Examiner(s): Cutler; Albert H
• Application Number:
  US12/352,321
• Publication Number:
  US 20090153717A1
• Time in Patent Office: 813 Days
• Field of Search: 348/241, 348/250, 348/294, 348/302, 348308-312, 250/208.1, 327/91, 327/94
• US Class Current: 348/241
• CPC Class Codes: H04N 25/672 between adjacent sensors or output registers for reading a single image
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array

Abstract

An CMOS active pixel sensor (APS) imaging system include circuitry to compensate for different analog offset levels from the CMOS pixel array. More specifically, the compensation is performed in the analog (charge) domain. A digital correction value, which may be measured as part of the operation or testing of the CMOS APS system, is provided to a offset correction block circuit, to generate an analog electrical signal. The analog electrical signal is supplied to a sample-and-hold circuit including a charge amplifier. The signal read from the pixel array, after conditioning through an analog signal chain, is also supplied to the charge amplifier, which has a linear transfer function and outputs the compensated signal.

Claims

1. An apparatus for processing a plurality of pixel signals, said apparatus comprising:

a first circuit, comprising a first set of sample capacitors, a second set of sample capacitors, and a charge amplifier, said charge amplifier being controllably coupled to said first and second set of sample capacitors, for producing an analog correction signal;

a second circuit comprising an amplifier, coupled to said first circuit, configured to receive an analog pixel signal from a third set of sample capacitors and, receive said analog correction signal from a fourth set of sample capacitors and produce a corrected analog signal by summing said analog pixel signal and said analog correction signal; and

an analog-to digital converter configured to convert said corrected analog signal into a digital signal.

2. The apparatus of claim 1, wherein each of the plurality of pixel signals is associated with a particular color and the analog correction signal is generated based on the color associated with each of the pixel signals.

3. The apparatus of claim 1, wherein said analog correction signal, said analog pixel signal, and said corrected analog signal comprise single ended signals.

4. The apparatus of claim 1, wherein each of said first, second, third, and fourth sets of sample capacitors comprise single capacitors.

5. The apparatus of claim 1, wherein said analog correction signal, said analog pixel signal, and said corrected analog signal comprise differential signals.

6. The apparatus of claim 1, wherein each of said first, second, third, and fourth sets of sample capacitors comprise a pair of sample capacitors.

7. An apparatus for correcting for an unwanted offset voltage from a pixel in a pixel array, comprising:

an offset correction block for receiving a digital correctional value and outputting an analog correction signal, said offset correction block comprising a first signal cell and a first skew cell; and

a sample-and-hold circuit, said sample-and-hold circuit further comprising a charge amplifier having a first input coupled to a first set of capacitors charged by an electrical signal produced by said pixel and a second input coupled to a second set of capacitors charged by the analog correction signal, and outputting a compensated signal as a linear function of the charge on said first and second sets of capacitors.

8. The apparatus of claim 7, wherein said first signal cell further comprises:

a programmable current source, for accepting a data portion of said digital correction value and producing a drive current proportional to the value of said data portion;

a resistor network, coupled to the programmable current source, and having at least two nodes at different potentials; and

a switching network having a pair of inputs coupled to said two nodes and a pair of outputs coupled to a pair of sampling capacitors, for accepting a sign bit portion of said digital correction value and for controllably inverting coupling or cross coupling said sampling capacitors with said two nodes, based on the sign bit portion of said digital correction value.

9. The apparatus of claim 7, wherein said analog correction signal, electrical signal produced by said pixel, and compensated signal are single ended signals and said first set of capacitors and second set of capacitors are each single capacitors.

10. The apparatus of claim 7, wherein said analog correction signal, electrical signal produce by said pixel, and compensated signal are differential signals and said first set of capacitors and second set of capacitors are each pairs of capacitors.

11. The apparatus of claim 7, wherein a skew signal is applied to an initial analog signal to produce the analog correction signal.

12. The apparatus of claim 7, wherein said first skew cell further comprises:

a constant current source, for accepting an enable signal and for producing a driving current if said enable signal is at a first logical state;

a resistor network, coupled to the constant current source, and having at least two nodes at different potentials; and

a switching network having a pair of inputs coupled to said two nodes and a pair of outputs coupled to a pair of sample capacitors, for accepting a polarity signal and for controllably inverting coupling or cross coupling said sample capacitors with said two nodes, based on the polarity signal.

13. The apparatus of claim 7, wherein the first signal cell is configured for producing an initial analog signal if the pixel is a green pixel.

14. The apparatus of claim 13, wherein the offset set correction block further comprises a second signal cell for producing the initial analog signal if the pixel is not a green pixel;

and

wherein said first signal cell is activated when the pixel is a green pixel and deactivated when the pixel is not a green pixel, and where the second signal cell is activated when then the pixel is not a green pixel and deactivated when the pixel is a green pixel.

15. The apparatus of claim 13, wherein the first skew cell is configured for producing a skew signal if the pixel is a green pixel and wherein said offset correction block further comprises:

a second signal cell for producing the initial analog signal if the pixel is not a green pixel; and

a second skew cell for producing the skew signal if the pixel is not a green pixel;

wherein said first signal cell and said first skew cell are activated when the pixel is a green pixel and deactivated when the pixel is not a green pixel, and where said second signal cell and said second skew cell are activated when then the pixel is not a green pixel and deactivated when the pixel is a green pixel.

16. The apparatus of claim 15, wherein said first and second skew cell each further comprise:

a constant current source, for accepting an enable signal and for producing a driving current if said enable signal is at a first logical state;

a resistor network, coupled to the constant current source, and having at least two nodes at different potentials; and

a switching network having a pair of inputs coupled to said two nodes and a pair of outputs coupled to a pair of sample capacitors, for accepting a polarity signal and for controllably inverting coupling or cross coupling said sample capacitors with said two nodes, based on the polarity signal.

17. An imaging system comprising:

a pixel array comprising a plurality of pixels;

a controller, for supplying digital correction value corresponding to each of said plurality of pixels;

a digital-to-analog converter, for converting an electrical signal output by one of said plurality of pixels into a digital signal;

a storage device for storing said digital signal; and

a circuit for correcting for an unwanted offset voltage in said pixel, said circuit for correcting further comprising;

an offset correction circuit, coupled to said controller and receiving said digital correctional value and outputting an analog correction signal comprising at least first and second signal cells and first and second skew cells; and

a sample-and-hold circuit, said sample-and-hold circuit further comprising a charge amplifier having a first input coupled to a first set of capacitors charged by an electrical signal produced by said pixel and a second input coupled to a second set of capacitors charged by the analog correction signal, and outputting a compensated signal as a linear function of the charge on said first and second sets of capacitors.

18. The imaging system of claim 17, wherein said first and second signal cells each comprise:

a programmable current source, for accepting a data portion of said digital correction value and producing a drive current proportional to the value of said data portion;

a resistor network, coupled to the programmable current source, and having at least two nodes at different potentials; and

a switching network having a pair of inputs coupled to said two nodes and a pair of outputs coupled to a pair of sampling capacitors, for accepting a sign bit portion of said digital correction value and for controllably inverting coupling or cross coupling said sampling capacitors with said two nodes, based on the sign bit portion of said digital correction value.

19. The imaging system of claim 17, wherein said first and second skew cells each comprise:

a constant current source, for accepting an enable signal and for producing a driving current if said enable signal is at a first logical state;

a resistor network, coupled to the constant current source, and having at least two nodes at different potentials; and

a switching network having a pair of inputs coupled to said two nodes and a pair of outputs coupled to a pair of sample capacitors, for accepting a polarity signal and for controllably inverting coupling or cross coupling said sample capacitors with said two nodes, based on the polarity signal.