Image sensors with pixel reset

• US 7,920,194 B2
• Filed: 03/18/2009
• Issued: 04/05/2011
• Est. Priority Date: 05/16/2000
• Status: Expired due to Term

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Inventors: Bock, Nikolai E.
• Primary Examiner(s): SELBY, GEVELL V
• Application Number:
  US12/406,175
• Publication Number:
  US 20090180017A1
• Time in Patent Office: 748 Days
• Field of Search: 348/294, 348/302, 348/308, 348/309, 348/311, 348/322, 348/323, 250/208.1
• US Class Current: 348/308
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS

Abstract

Techniques for use with image sensors include transferring a signal level from an active sensor pixel to a readout circuit, performing a flushed reset of the pixel, and isolating the pixel from the readout circuit during resetting of the pixel.

Claims

1. An imager device comprising:

an array of pixels organized into a plurality of rows and columns, each pixel comprising a photosensitive element, a source follower transistor having a gate terminal coupled to an output of the photosensitive element, a row select switch coupled between a column output line and the source follower transistor, and a reset switch connected to the photosensitive element;

a plurality of readout circuits, each readout circuit being associated with and coupled to a respective column of pixels, each readout circuit comprising a load transistor associated with source follower transistors in the pixels of the associated column, each readout circuit further comprising a hard reset circuit coupled to a drain of the reset transistor in the pixels of the associated column and an enabling transistor connected between the output line and the load transistor; and

a controller adapted to;

enable the row select switch of each pixel in a selected row to cause each pixel in the selected row to transfer a first voltage representing an amount of light impinging on a respective pixel during an integration period to the respective readout circuit, disable the row select switch of each pixel in the selected row to electrically disconnect the pixels in the selected row from the respective readout circuit, activate the hard reset circuits of the plurality of readout circuits to perform a hard reset of the pixels in the selected row, enable the reset transistor of each pixel in the selected row to perform a soft reset of the pixels in the selected row, and enable the row select switch of each pixel in the selected row to electrically connect the pixels in the selected row to the associated readout circuit and transfer a second voltage from the pixels in the selected row to the readout circuit, the second voltage representing a soft reset level for the pixels.

2. The imager device of claim 1, wherein the controller disables the enabling transistor of the plurality of readout circuits for preventing a parasitic output capacitance from discharging through the load transistor of the readout circuits during the hard and soft reset operations.

3. The imager device of claim 1, wherein the hard reset discharges a power supply capacitance present at a node coupled to the drain of each reset transistor of the pixels in the selected row.

4. The imager device of claim 1, wherein the hard reset circuit of each readout circuit comprises:

a p-channel transistor connected between a power source and the drain of the respective reset transistor;

a first n-channel transistor connected between the drain of the respective reset transistor and a ground potential; and

a second n-channel transistor connected across the p-channel transistor and having a gate terminal and a drain terminal connected to the power source, wherein the controller activates the hard reset circuit by generating a control signal that enables the p-channel and first n-channel transistors.

5. An imager integrated circuit comprising:

means for transferring a signal level from a pixel circuit to a readout circuit;

means for performing a flushed reset of the pixel circuit;

means for electrically isolating the pixel circuit from the readout circuit during a period required to perform the flushed reset of the pixel circuit, wherein the isolating occurs during an entirety of each period required to perform the flushed reset of the pixel circuit; and

means for preventing a parasitic output capacitance from discharging through a load transistor in the readout circuit during the reset, wherein said means for preventing the parasitic output capacitance from discharging comprises means for opening a switch coupled between the load transistor and an output line connected to the pixel circuit.

6. An imager integrated circuit comprising:

means for transferring a signal level from a pixel circuit to a readout circuit;

means for performing a flushed reset of the pixel circuit; and

means for electrically isolating the pixel circuit from the readout circuit during a period required to perform the flushed reset of the pixel circuit, wherein the isolating occurs during an entirety of each period required to perform the flushed reset of the pixel circuit, wherein said isolating means comprises means for disabling a row select transistor switch in the pixel circuit when the pixel circuit is being reset.

7. An imager integrated circuit comprising:

means for transferring a signal level from a pixel circuit to a readout circuit;

means for performing a flushed reset of the pixel circuit; and

means for electrically isolating the pixel circuit from the readout circuit during a period required to perform the flushed reset of the pixel circuit, wherein the isolating occurs during an entirety of each period required to perform the flushed reset of the pixel circuit, wherein said means for isolating the pixel circuit comprises means for disabling a row selection switch for the duration of the flushed reset, and said circuit further comprises means for preventing a parasitic output capacitance from discharging through a load transistor in the readout circuit during the reset.

8. An imager integrated circuit comprising:

means for transferring a signal level from a pixel circuit to a readout circuit;

means for performing a flushed reset of the pixel circuit; and

means for electrically isolating the pixel circuit from the readout circuit during a period required to perform the flushed reset of the pixel circuit, wherein the isolating occurs during an entirety of each period required to perform the flushed reset of the pixel circuit, wherein said means for performing a flushed reset comprises means for performing a hard reset followed by a soft reset.

9. An imager device comprising:

an array of pixels, each pixel being associated with a row and a column in the array, each pixel including a reset switch and a row selection switch;

a plurality of readout circuits, each readout circuit being associated with and coupled to a respective column of pixels in the array; and

a controller electrically connected to the array and readout circuits, said controller adapted to generate a first control signal to enable the row selection switches in a selected row of pixels to transfer signal levels from the pixels in the selected row to the associated readout circuits, said controller being adapted to generate a second control signal subsequent to the first control signal to enable the reset switches in the selected row of pixels, said controller being adapted to remove the first control signal to disable the row selection switches in the selected row of pixels and to isolate the pixels from the associated readout circuits during a period required to perform the resetting of the pixels in the selected row, wherein the isolating occurs during an entirety of each period required to perform the resetting of the pixels and wherein each pixel further comprises a source-follower transistor coupled to a photodiode and each readout circuit comprises;

a load transistor for the source-follower transistor in the pixels associated with the readout circuit; and

an enable switch coupled in series with the load transistor and coupled between the load transistor and an output of the pixels in the associated columns, wherein the controller is adapted to provide a third control signal for disabling the enable switch during resetting of the pixels.

10. The device of claim 9, wherein each readout circuit comprises hard reset circuitry for performing a flushed reset of the pixels associated with that readout circuit when the controller generates a third control signal.

11. The device of claim 10, wherein the controller generates the third control signal while generating the second control signal that enables the reset switches in the selected row of pixels.

14. The imager device of claim 9, wherein the controller disables the enabling transistor for preventing a parasitic output capacitance from discharging through the load transistor of the readout circuit during the flushed reset.

12. An imager device comprising:

an array of pixels, each pixel being associated with a row and a column in the array, each pixel including a reset switch and a row selection switch;

a plurality of readout circuits, each readout circuit being associated with and coupled to a respective column of pixels in the array; and

a controller electrically connected to the array and readout circuits, said controller adapted to generate a first control signal to enable the row selection switches in a selected row of pixels to transfer signal levels from the pixels in the selected row to the associated readout circuits, said controller being adapted to generate a second control signal subsequent to the first control signal to enable the reset switches in the selected row of pixels, said controller being adapted to remove the first control signal to disable the row selection switches in the selected row of pixels and to isolate the pixels from the associated readout circuits during a period required to perform the resetting of the pixels in the selected row, wherein the isolating occurs during an entirety of each period required to perform the resetting of the pixels, wherein each readout circuit comprises hard reset circuitry for performing a flushed reset of the pixels associated with that readout circuit when the controller generates a third control signal and wherein the reset switch comprises a reset transistor and the hard reset circuitry comprises;

a p-channel transistor connected between a power source and the drain of the respective reset transistor, the p-channel transistor having a gate terminal connected to receive the third control signal;

a first n-channel transistor connected between the drain of the respective reset transistor and a ground potential, the first n-channel transistor having a gate terminal connected to receive the third control signal; and

a second n-channel transistor connected across the p-channel transistor and having a gate terminal and a drain terminal connected to the power source, wherein the hard reset circuitry is activated when the third control signal enables the p-channel and first n-channel transistors.

13. An imager device comprising:

an array of pixels, each pixel being associated with a row and a column in the array, each pixel including a reset switch and a row selection switch;

a plurality of readout circuits, each readout circuit being associated with and coupled to a respective column of pixels in the array; and

a controller electrically connected to the array and readout circuits, said controller adapted to generate a first control signal to enable the row selection switches in a selected row of pixels to transfer signal levels from the pixels in the selected row to the associated readout circuits, said controller being adapted to generate a second control signal subsequent to the first control signal to enable the reset switches in the selected row of pixels, said controller being adapted to remove the first control signal to disable the row selection switches in the selected row of pixels and to isolate the pixels from the associated readout circuits during a period required to perform the resetting of the pixels in the selected row, wherein the isolating occurs during an entirety of each period required to perform the resetting of the pixels, wherein each readout circuit comprises hard reset circuitry for performing a flushed reset of the pixels associated with that readout circuit when the controller generates a third control signal and wherein the hard reset discharges a power supply capacitance present at a node coupled to the drain of the pixel reset transistor.